RISC-V Advanced Interrupt Architecture

Describes an Advanced Interrupt Architecture for RISC-V systems.

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RISC-V IOMMU Architecture

Describes an Input-Output Memory Management Unit (IOMMU) that connects direct-memory-access-capable Input/Output (I/O) devices to system memory.

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RISC-V Platform-Level Interrupt Controller

Delineates the operational parameters for a platform-level interrupt controller on RISC-V.

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RISC-V Server SOC

Defines a standardized set of capabilities that portable system software such as operating systems and hypervisors, can rely on being present in a RISC-V server SoC.

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Efficient Trace for RISC-V

Specifies the signals between the RISC-V core and the encoder, compressed branch trace algorithm, and the packet format used to encapsulate the compressed branch trace information to implement processor tracing.

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RISC-V Capacity and Bandwidth QoS Register Interface

Specifies:

1. QoS identifiers to identify workloads that originate requests to the shared resources.

2. Access-type identifiers to accompany request to access a shared resource to allow differentiated treatment of each access-type.

3. Register interface for capacity allocation in controllers such as shared caches, directories, etc.

4. Register interface for capacity usage monitoring.

5. Register interface for bandwidth allocation in controllers such as interconnect and memory
   controllers.

6. Register interface for bandwidth usage monitoring.

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The RISC-V Debug

Outlines a standard architecture for debug support on RISC-V hardware platforms. This architecture allows a variety of implementations and tradeoffs, which is complementary to the wide range of RISC-V implementations. At the same time, this specification defines common interfaces to allow debugging tools and components to target a variety of hardware platforms based on the RISC-V ISA.

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RISC-V N-Trace (Nexus-based Trace)

Implements the IEEE-5001 Nexus Standard tailored to support the trace of RISC-V ISA cores, harts and SoC/MCU designs.

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RISC-V RERI Architecture

Augments Reliability, Availability, and Serviceability (RAS) features in the SoC with a standard mechanism for reporting errors by means of a memory-mapped register interface to enable error reporting. Additionally, this specification supports software-initiated error logging, reporting, and testing of RAS handlers. Lastly, this specification provides maximal flexibility to implement error handling and coexists with RAS frameworks defined by other standards such as PCIe and CXL.

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RISC-V Trace Connectors

Adds trace signals to connectors described in RISC-V External Debug Support and provides a small, optional extension to connectors described in and MIPI Debug & Trace Connectors Recommendations White Paper, Version 1.20, 2 July 2021.

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RISC-V Trace Control Interface

Presents a standardized control interface for RISC-V trace infrastructure (such as trace encoders, trace funnels, trace sinks) for the Efficient Trace for RISC-V specification and for the RISC-V N-Trace (Nexus-based Trace) specification. Standardized control interface allows trace control software development tools to be used interchangeably with any RISC-V device implementing processor and/or data trace.

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Unformatted Trace & Diagnostic Data Packet Encapsulation for RISC-V

Defines an encapsulation format suitable for use with a variety of transport mechanisms, including but not limited to AMBA Advanced Trace Bus (ATB) and Siemens' Messaging Infrastructure.

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RISC-V Boot and Runtime Services (BRS)

Defines a standardized set of software capabilities, that portable system software, such as operating systems and hypervisors, can rely on being present in an implementation to utilize in acts of device discovery, OS boot and hand-off, system management, and other operations.

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RISC-V Functional Fixed Hardware

Provides additional system specification for RISC-V systems which use Advanced Configuration and Power Interface (ACPI), specifically for some ACPI object fields of type “Resource Descriptor”.

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RISC-V IO Mapping Table

Provides information about the RISC-V IOMMU and the relationship between the IO topology and the IOMMU in ACPI based RISC-V platforms. The RIMT identifies which components are behind IOMMU and how they are connected together.

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RISC-V Platform Management Interface (RPMI)

Describes an OS-agnostic, firmware-agnostic, scalable and extensible interface for platform management and control from dedicated microcontrollers (also referred to as platform microcontroller or PuC).

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RISC-V Semihosting

Defines the semihosting binary interface for RISC-V platforms.

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RISC-V Supervisor Binary Interface

The RISC-V Supervisor Binary Interface, allows supervisor-mode (S-mode or VS-mode) software to be portable across all RISC-V implementations by defining an abstraction for platform (or hypervisor) specific functionality. The design of the SBI follows the general RISC-V philosophy of having a small core along with a set of optional modular extensions.

Version 3.0 adds PMU event information and base event type; new extensions for MPXY, DBTR, FWFT, and SSE; additional error codes; and clarifications in the set_timer function and IPI and RFENCE error codes.

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RISC-V UEFI Protocol

Details all new UEFI protocols required only for RISC-V platforms.

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RISC-V ABIs

Provides the processor-specific application binary interface document for RISC-V.

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RISC-V Vector C Intrinsic

Provide user interfaces in the C language level to directly leverage the RISC-V Vector Extensions with assistance from the compiler in handling instruction scheduling and register allocation. The intrinsics also free users from responsibility of maintaining the correct configuration settings for the vector instruction executions.

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