2026

August   

• ​Aug 10, 2026 ���? Public review opens for the RVA23.1 and RVB23.1 Profiles. The 30-day public review period runs from August 10 to September 9, 2026. Both profiles are published at v0.9 for review: RVA23.1 and RVB23.1. Feedback goes to isa-dev or the riscv-isa-manual issue tracker, with the profile text moving into the combined ISA manual via PR #3298. Announcement: tech-announce #778. RVS-4180, RVS-4184.

• ​Aug 10, 2026 ?���️ Toolchains SIG elects its Chair and Vice-Chair for the 2026–2027 term. The Toolchains SIG election closed with 6 ballots cast. Christoph Müllner (VRULL) was re-elected Chair by approval vote, 6 Approve to 0 Object and 0 Abstain. Sam Elliott (Qualcomm) was elected Vice-Chair by Plurality with 5 votes to 1 for Dandan Xu (ISCAS). The new term is effective immediately and continues to July 31, 2027. RVC-892, RVG-11.

• ​Aug 6, 2026 🗳️ HPC SIG elects its Chair and Vice-Chair for the 2026–2027 term. The High Performance Computing SIG election closed with 4 of the 5 eligible ballots returned (4 valid, 0 empty). Nick Brown (EPCC) was re-elected Chair by Plurality with 4 votes to 0 for Ji Qi (ISCAS). Doug Norton (Inspire Semiconductor, Inc.) was elected Vice-Chair by Instant Runoff with 4 first choices to 0 for Ji Qi (ISCAS). The new term is effective immediately and continues to July 31, 2027. RVC-853, RVG-12.

• ​Aug 4, 2026 🗳️ Privileged IC approves the Timing Fences Ratification Plan. The Privileged ISA Committee approval vote concluded with 3 of the 4 eligible ballots returned: 2 Approve, 1 Object and 0 Abstain. The quorum of 3 was met and the required majority achieved, so the Timing Fences Ratification Plan is approved. RVS-3569, RVS-3573.

• ​Aug 3, 2026 🗳️ ISA Infrastructure HC elects its Chair and Vice-Chair for the 2026–2027 term. The ISA Infrastructure Horizontal Committee election closed on August 3, 2026 with 4 of the 5 eligible ballots returned. Wei Wu (KUBUDS Tech) was confirmed as Chair with 4 Approve, 0 Object and 0 Abstain, and Henrik Gustafsson (Qualcomm) was confirmed as Vice-Chair on the same tally. The new term is effective immediately and continues to July 31, 2027. RVC-747, RVG-32.

• ​Aug 3, 2026 🗳️ Server SoC II TG elects its first Chair and Vice-Chair. The Server SoC II Task Group election closed with 8 of the 9 eligible ballots returned, both seats decided by Instant Runoff Voting. David Kruckemyer (Qualcomm) was elected Chair with 5 first choices to 3 for Haimeng Wang (ZTE), ahead of Chenchen Ji (ISCAS). In a five-candidate Vice-Chair race over 7 valid votes and 1 empty, Haimeng Wang (ZTE Corporation) was elected in the fourth round with 4 votes to 3 for Shan Liu (Damo Academy, Alibaba Group), after Fei Zhang, Wang Yang and Zhe Qiao (all ISCAS) were eliminated. The new term is effective immediately and continues to July 31, 2027. RVC-624, RVG-624.

• ​Aug 3, 2026 🗳️ CSC Operations WG elects a Vice-Chair; the Chair seat stays open. The Certification Steering Committee Operations Working Group election ended early with all 3 eligible ballots returned. James Shi (Alibaba) was elected Vice-Chair with 2 votes to 1 for Xiaohan Ma (ISCAS), counted using Plurality/FPTP/SNTV. The Chair position remains open and will be covered by RISC-V staff until a candidate steps forward.

• ​Aug 3, 2026 🗳️ PQC TG confirms its Chair and Vice-Chair for the new term. The Post-Quantum Cryptography Task Group election closed with 7 of the 8 eligible ballots returned. Markku-Juhani Saarinen (Tampere University) was confirmed as Chair with 7 Approve, 0 Object and 0 Abstain, and Nicolas Brunie (SiFive) was confirmed as Vice-Chair with 7 Approve, 0 Object and 0 Abstain. The new term is effective immediately and runs through July 31, 2027. RVC-832, RVG-84.

• ​Aug 3, 2026 🗳️ Packed SIMD TG confirms its Chair and elects a Vice-Chair. The Packed Single Instruction, Multiple Data Task Group election closed with 7 of the 9 ballots returned. Rich Fuhler (Andes) was confirmed as Chair with 7 Approve, 0 Object and 0 Abstain under Plurality/FPTP/SNTV. In the Vice-Chair election, decided by Instant Runoff Voting over 6 valid votes and 1 empty, Jiawei Chen (ISCAS) was elected with 4 first choices to 2 for Rich Fuhler. The new term runs to July 31, 2027. RVC-826, RVG-129.

• ​Aug 3, 2026 🗳️ RPMI TG returns its Chair and Vice-Chair for a new term. The Platform Management Interface Task Group election closed with 2 of the 3 eligible ballots returned. Ley Foon Tan (Individual Member) was re-elected Chair with 2 votes to 0 over Rahul Pathak, counted using Plurality/FPTP/SNTV, and Rahul Pathak (Qualcomm) was re-elected Vice-Chair with 2 first choices under Instant Runoff Voting. The new term is effective immediately and continues to July 31, 2027. RVC-821, RVG-151.

• ​Aug 3, 2026 🗳️ IOPMP TG elects a new Chair and Vice-Chair. The I/O Physical Memory Protection Unit Task Group election closed with 5 of the 8 eligible ballots returned. Channing Tang (NVIDIA), previously Vice-Chair, was confirmed as Chair with 5 Approve, 0 Object and 0 Abstain, succeeding Paul Ku (Andes). Alvin Chang (Andes Technology Corporation) was confirmed as Vice-Chair with 5 Approve, 0 Object and 0 Abstain. Both were counted using Plurality/FPTP/SNTV. The new term is effective immediately and runs through July 31, 2027. RVC-816, RVG-56.

• ​Aug 3, 2026 🗳️ SPMP TG confirms its Chair and Vice-Chair for the new term. The S-mode Physical Memory Protection Task Group election closed with 4 of the 5 eligible ballots returned. Bicheng Yang (Shanghai Jiao Tong University) was confirmed as Chair with 4 Approve, 0 Object and 0 Abstain, and Sandro Pinto (Universidade do Minho) was confirmed as Vice-Chair with 4 Approve, 0 Object and 0 Abstain. Both were counted using Plurality/FPTP/SNTV. The new term is effective immediately and continues to July 31, 2027. RVC-812, RVG-100.

July   

• ​Jul 30, 2026 ?️ Community and Individual Members confirm their TSC Representative. The confirmation vote for the Community/Individual Member TSC Representative closed with 66 of 286 ballots returned. Guy Lemieux was confirmed with 61 Approve, 0 Object and 5 Abstain, so no member objected. He serves as the Community/Individual Member TSC Representative for the coming term.

• ​Jul 30, 2026 🗳️ Strategic Members elect their two TSC Representatives. The election for the 2 Strategic Member TSC Representatives closed with 46 of 167 ballots returned. Debbie Marr (AheadComputing) was elected with 35 votes and Tariq Kurd (Codasip) with 21, ahead of Weiwei Li (Kubuds) with 20. Both serve as the TSC Representatives for the Strategic membership for the coming term. Note: the OpaVote results list 170 total votes, which includes 3 members whose email addresses changed during voting. The old addresses were disabled and could not vote, but the tool still lists them.

• ​Jul 30, 2026 🗳️ Fast Interrupts (CLIC) TG elects its Chair and Vice-Chair for the 2026–2027 term. The Fast Interrupts (CLIC) TG election closed early with all 6 eligible ballots returned. Christian Herber (NXP) was re-elected Chair 5–1 over Alexey Khomich (Globalfoundries) under Plurality/FPTP. James Ball (Microchip) was confirmed as Vice-Chair with 4 Approve, 0 Object and 2 Abstain. Both terms are effective immediately and run through July 31, 2027. RVC-807, RVG-63.

• ​Jul 29, 2026 🗳️ Technology HC re-elects its Chair and Vice-Chair for the 2026–2027 term. The Technology Horizontal Committee election concluded with 2 of the 3 eligible votes submitted. Philipp Tomsich (VRULL) was approved as Chair with 2 Approve, 0 Object and 0 Abstain, and Xiaofei Gong (ISCAS) was approved as Vice-Chair with 1 Approve, 0 Object and 1 Abstain. The new term is effective immediately and continues to July 31, 2027. RVC-766, RVG-104.

• ​Jul 28, 2026 🗳️ Privileged Software HC re-approves Anup Patel as Chair for the 2026–2027 term. The Chair-only election concluded with 3 of the 4 eligible ballots returned and unanimous approval: 3 Approve, 0 Object, 0 Abstain. Anup Patel (Qualcomm) continues as Chair, effective immediately through July 31, 2027. The Vice-Chair seat remains vacant. RVC-752, RVG-39.

• ​Jul 28, 2026 🗳️ SOC Infrastructure HC elects its Chair and Vice-Chair for the 2026–2027 term. The election concluded with 7 of the 8 eligible ballots returned. Henrik Gustafsson (Qualcomm) was approved as Chair with 6 Approve, 0 Object and 1 Abstain. In a two-candidate Vice-Chair race, Iain Robertson (Siemens EDA) was elected with 6 votes to 1 for Yudong Liu (ISCAS). The new term is effective immediately and continues to July 31, 2027. RVC-763, RVG-88.

• ​Jul 28, 2026 🗳️ High Assurance Cryptography TG re-elects its Chair and Vice-Chair for the 2026–2027 term. All 6 eligible ballots were returned. Ruud Derwig (GlobalFoundries) was approved as Chair with 6 Approve, 0 Object and 0 Abstain, and Roberto Avanzi (Qualcomm) was elected Vice-Chair with 6 votes to 0 for Wang Yang (ISCAS). The new term is effective immediately and continues to July 31, 2027. RVC-792, RVG-145.

• ​Jul 28, 2026 🗳️ Floating Point SIG re-elects its Chair and Vice-Chair for the 2026–2027 term. The Floating Point SIG election closed early with all 4 eligible ballots returned. Nicolas Brunie (SiFive) was re-elected Chair 4–0 over Kenneth Rovers (imec) under Plurality/FPTP. In the Vice-Chair race, decided by Instant Runoff Voting among three candidates, Kenneth Rovers (imec) was elected with 3 of 4 first-choice votes. Both terms are effective immediately and run through July 31, 2027. RVC-906, RVG-123.

• ​Jul 28, 2026 🗳️ Security HC elects its Chair and Vice-Chair for the 2026–2027 term. The Security Horizontal Committee election closed with 11 of the 14 eligible ballots returned. Andrew Dellow (Qualcomm) was confirmed as Chair with unanimous approval (11 Approve, 0 Object, 0 Abstain; Plurality/FPTP). The Vice-Chair race was decided by Instant Runoff Voting among four candidates, with Geoffrey Thorpe (MIPS) elected 5–4 over Nick Kossifidis (FORTH) in the final round. Both terms are effective immediately and end July 31, 2027. RVC-756, RVG-68.

• ​Jul 28, 2026 🗳️ SOC Infrastructure HC approves the Freeze Milestone for 3 Fast Track E-Trace extensions. The SOC Infrastructure Horizontal Committee approval vote closed with 7 of the 8 ballots returned and unanimous approval on each item (7 Approve, 0 Object, 0 Abstain; Plurality/FPTP): Implicit Return, Data Trace of Multiple-Memory Access and Compare and Swap, and Standard Support Packet — all Fast Track extensions to E-Trace. With the Freeze Milestone approved, the documents may be updated and posted for Public Review.

• ​Jul 25, 2026 📝 ARC Minutes (meeting 2026-07-11, published 2026-07-25). A newly updated CHERI specification was received and review of it has begun. The Zijf proposal (32-bit far jumps and calls) was approved to be pursued as a fast track. The ARC also discussed GitHub issue #3258, on the definition of the Ssstrict extension and its applicability with respect to reserved encodings within standard instructions, and posted a response to the issue. Source: tech-privileged "ARC minutes, 2026-07-11".

• ​Jul 23, 2026 ?️ TSC approves sending the SPMP specification to the Board for ratification. The TSC approval vote closed with all 23 ballots returned: 20 Approve, 0 Object, 3 Abstain (Plurality/FPTP), exceeding the required majority. The S-mode Physical Memory Protection (SPMP) specification will be presented to the Board of Directors for ratification at the August meeting. RVS-921.

• ​Jul 22, 2026 ? ARC Minutes (meeting 2026-07-15, published 2026-07-22). The Zabhlrsc extension was granted ARC approval. On Sscpuutil (CPU Utilization), the ARC provided additional feedback to the proposers related to virtualization of the feature. On Zilx (indexed loads), the ARC reviewed the draft spec, recommended minor changes and returned a revised instruction encoding to the proposers. The ACLINT fast track was reviewed, but the ARC could not determine that any changes had been made in response to the earlier feedback (early 2022) that led to the proposal being rejected; that feedback is being relayed to the new proposers along with a suggested path forward. The ARC also reviewed the Secure External Debug TG response to its earlier feedback and will communicate further feedback to the TG. Source: tech-privileged "ARC Meeting Minutes 2026-07-15".

• ​Jul 20, 2026 ? RVM Profile TG launches a privileged/security survey for the RVM10 profile. The RVM Profile Task Group opened a short survey to converge on four privileged and security extension decisions for the RVM10 profile: Ssstrict, Smrnmi, Smdbltrp, and PMP (Smpmp + Smepmp). Each question ships with its context and tradeoffs; responses feed directly into the TG discussion. Survey.

• ​Jul 15, 2026 ?️ Applications & Tools HC elects its Chair and Vice-Chair for 2026. The Applications & Tools Horizontal Committee election closed early on July 15 with all 4 ballots returned. Philipp Tomsich (VRULL GmbH) was re-elected Chair (4–0 over Yunxiang Jia), and Yunxiang Jia (ZTE Corporation) was approved as Vice-Chair (4 Approve / 0 Object / 0 Abstain), succeeding David Chen (StreamComputing). Both serve a one-year term through 2027-07-15. RVG-4.

• ​Jul 14, 2026 🗳️ Privileged ISA Committee re-elects its Chair and Vice-Chair. The election concluded early with all 4 votes returned and unanimous approval of both seats. Greg Favor (Qualcomm) was approved as Chair and Andrew Waterman (SiFive) as Vice-Chair, each with 4 Approve, 0 Object and 0 Abstain. RVC-773, RVG-59.

• ​Jul 14, 2026 🗳️ Unprivileged ISA Committee elects its Chair and Vice-Chair. The election concluded early with all 7 votes submitted. Krste Asanović (SiFive) was approved as Chair with 6 Approve, 0 Object and 1 Abstain. The Vice-Chair seat was decided by Instant Runoff Voting, with Earl Killian (Aril Inc.) elected on first choices, 6 votes to 1. RVC-777, RVG-122.

• ​Jul 13, 2026 🎤 RISC-V Technical Session announced for Thursday, July 16. Alexander Strack (University of Stuttgart) presents “Is RISC-V Ready for Machine Learning?”, a cross-architecture evaluation of machine learning and scientific-computing workloads (HPX) across RISC-V, ARM, and x86. Event details.

• ​Jul 13, 2026 📢 Call for Papers: RV-CONVERGE 2026. Workshop on RISC-V for the HPC and AI Convergence Era, co-located with CARLA 2026 (workshop day September 22). Topics include RVV and custom AI accelerators, HPC library and compiler ports, performance-per-watt vs x86/ARM, and RISC-V adoption across Latin America. Submissions due July 19. carlaconference.org/rv-converge.

• ​Jul 13, 2026 ✅ PQC TG approves the Development Complete Milestone. The PQC TG Development Milestone Approval vote for the Post-Quantum Cryptography (Keccak) specification closed with all 8 eligible ballots returned (8 Approve / 0 Object / 0 Abstain, Plurality/FPTP/SNTV). Governing Committee informal approval will be requested next, after which the milestone completes and the specification proceeds to Internal Review. RVS-2360.

• ​Jul 9, 2026 📝 ARC Minutes (meeting 2026-07-01, published 2026-07-09). In response to a request from the Packed SIMD (P) TG, the ARC discussed whether the P extension should require misaligned load/store, and what that would mean, or should merely strongly recommend it. Feedback will be communicated to the P TG. The ARC also looked at the Zilx fast-track proposal and will provide feedback to the authors, particularly in the area of instruction encodings. Source: tech-unprivileged "ARC minutes 2026-07-01".

• ​Jul 8, 2026 ✅ CLIC achieves the Stabilization Milestone. The CLIC TG Stabilization Milestone Approval vote for the Advanced Core-Local Interrupt Controller specification closed early with all 5 ballots returned (3 Approve, 1 Object, 1 Abstain); the required majority was exceeded. RVS-1017 moves to Freeze.

• ​Jul 2, 2026 ✅ TSC approves the DTPM SIG Updated Charter — The OpaVote "TSC Vote to Approve the Debug, Trace, and Performance Monitoring (DTPM) SIG Updated Charter" concluded with 23 ballots returned: 21 Approve / 1 Object / 1 Abstain (Plurality/FPTP/SNTV) — the required 2/3 majority is exceeded and the updated charter is approved. DTPM SIG (RVG-89).

• ​Jul 2, 2026 📁 TSC disbands the Performance Analysis SIG — The OpaVote "Technical Steering Committee Vote to Disband the Performance Analysis SIG" concluded with 24 ballots returned: 24 Approve / 0 Object / 0 Abstain (Plurality/FPTP/SNTV) — unanimous approval, the required 2/3 majority is exceeded and the Performance Analysis SIG is disbanded. Performance Analysis SIG (RVG-8).

• ​Jul 2, 2026 ✅ TSC approves the AI/ML SIG Updated Charter — The OpaVote "Technical Steering Committee Vote to Approve the AI/ML SIG Updated Charter" concluded with 23 ballots returned: 23 Approve / 0 Object / 0 Abstain (Plurality/FPTP/SNTV) — quorum met, unanimous approval, the required 2/3 majority exceeded, and the updated charter is approved. AI/ML SIG (RVG-5).

June   

• ​Jun 24, 2026 ✅ ARC approves Zilx (RISC-V Integer Indexed Load) as a Fast Track. Register-register indexed integer loads (unscaled and scaled, plus RV64 .uw variants), proposed by Pengcheng Wang (ByteDance) out of the Scalar Efficiency SIG. Recorded in the ARC minutes, 2026-06-24.

• ​Jun 24, 2026 ✅ ARC approves Sscpuutil as a Fast Track — At its 2026-05-20 meeting (minutes published 2026-06-24), the Architecture Review Committee (ARC) approved the CPU Utilization Counter Extension (Sscpuutil) to be pursued as a fast-track extension, with a number of suggestions to be communicated to the proposers. ARC review thread.

• ​Jun 15, 2026 📅 Tech Session announced — Code Size Reduction by Advanced Near Addressing Modes — Dr. Kajetan Nürnberger (Infineon) will present his work on a RISC-V addressing-mode approach that reduces global-variable access from two instructions to one, helping shrink code size and improve performance in real-time embedded systems (a custom technique being explored, not a standard extension). Event & registration · paper: arXiv:2605.25602.

• ​Jun 12, 2026 🎉 Ziccid Ratified — The Instruction/Data Coherence and Consistency Extension (Ziccid, RVS-3933) has been ratified by the Board of Directors, completing the fast-track lifecycle (ISA extension, prose-only, driven by Andrew Waterman). The specification is integrated into the ISA manual via riscv-isa-manual PR #2598.

• ​Jun 12, 2026 🎉 RQSC v1.0.0 Ratified release published — Following the TSC approval vote (17 Approve / 0 Object / 4 Abstain) and Board ratification, version v1.0.0 (Ratified) of the RISC-V Quality of Service Controllers Table (RQSC) ACPI Specification is published: GitHub release v1.0.0 with the ratified PDF (title page: v1.0.0, 2026-06-12, Ratified). The PDF is also attached to RVS-3826.

• ​Jun 11, 2026 TSC approved sending the RQSC Specification to the Board for Ratification — The OpaVote "TSC Approval to Send Quality of Service Controllers Table (RQSC) Spec to Board for Ratification" closed with 21 of 26 ballots returned: 17 Approve / 0 Object / 4 Abstain (Plurality/FPTP/SNTV) — required majority exceeded. The RISC-V Quality of Service Controllers Table (RQSC) Specification (RVS-3826) will be presented to the Board for Ratification.

• ​Jun 6, 2026 Release of version 0.12 of the Sail RISC-V Golden Model — Highlights: the pointer masking extensions, improved performance, more configuration parameters, and stricter handling of register constraints in the vector extension. Release 0.12 · ChangeLog.

• ​Jun 8, 2026 ?️ Open Calls for Candidates extended one week for RISC-V Summit Europe — All open 2026 Chair/Vice-Chair Calls for Candidates had their deadlines slipped by one week so the Summit does not cut into the nomination window. New application deadlines: June 22 (Horizontal Committees) and June 23 (SIGs, TGs, ISA Committees); elections and results follow the week of July 6–7. Source: RVC Call for Candidates.

• ​Jun 5, 2026 ? ARC Minutes (meeting 2026-06-03, published 2026-06-05) — The ARC began review of the External Debug Security spec (to continue the week after RISC-V Summit Europe). On IOPMP, the ARC held a live discussion with the IOPMP chairs on the more notable review feedback and the bigger questions about the intent of the spec; that feedback, together with the documented prior review comments, has now been provided, and the ARC awaits an updated spec. Source: tech-chairs "ARC minutes, 2026-06-3".

• ​Jun 3, 2026 📝 ARC Minutes (meeting 2026-05-27, published 2026-06-03) — The ARC approved the three E-Trace fast-track extensions — Standard Support Packet, Implicit Return, and Data Trace of Multiple Memory Access and CAS — which have completed ARC review. The ARC continued discussion of the Sscpuutil fast-track proposal and gave additional feedback to the authors, and began review of the most recent IOPMP draft spec. Source: tech-unprivileged "ARC minutes, 2026-05-27".

• ​Jun 2, 2026 Parameters SIG Call for Candidates OPENED — A Chair and Vice-Chair Call for Candidates launched for the forming Parameters SIG (RVG-931, governed by the ISA Infrastructure HC), running through ​Jun 16, 2026. Announced to sig-parameters (cc isa-infra + tech-announce). Nominate via the RISC-V Leadership Application form.

• ​Jun 2, 2026 SIG elections OPENED (15 SIGs) — Calls for Candidates launched for Chair and Vice-Chair across 15 RISC-V Special Interest Groups whose chair terms had lapsed: HPC, Hypervisors, DTPM, Performance Modeling, Android, Architecture Test, Trusted Computing, Documentation, Toolchains, AI/ML, Vector, Floating Point, Runtime Integrity, Soft CPU, and Functional Safety. Running through ​Jun 16, 2026. One announcement per SIG was sent to its list (cc its governing committee + tech-announce); RVC tracking issues and Confluence CfC pages created for each. Nominate via the RISC-V Leadership Application form.

• ​Jun 2, 2026 SIG leadership calls OPENED — Calls for Candidates launched for the UnifiedDB SIG (Chair), Scalar Efficiency SIG (Chair), and Performance Analysis SIG (Vice-Chair), running through ​Jun 16, 2026. The two Chair vacancies follow Derek Hower’s departure (Lu Liu and Pengcheng Wang remain Vice-Chairs). Announcements sent per SIG to its list (cc governing committee + tech-announce). Nominate via the RISC-V Leadership Application form.

• ​Jun 2, 2026 Task Group elections OPENED — A Call for Candidates launched for Chair and Vice-Chair across 11 RISC-V Task Groups (CoVE, External Debug Security, HAC, SmMTT, CoVE-IO, Fast Interrupts/CLIC, SPMP, IOPMP, RPMI, Packed SIMD-P, PQC), running through ​Jun 16, 2026. One announcement per TG was sent to its mailing list (cc its governing committee + tech-announce); RVC tracking issues and Confluence CfC pages were created for each. CoVE’s prior Vice-Chair call (RVC-706) was superseded and its 5 candidates carried over. Nominate via the RISC-V Leadership Application form.

• ​Jun 2, 2026 ISA Committee elections OPENED — A combined Call for Candidates launched for Chair and Vice-Chair of both RISC-V ISA Committees (Privileged, Unprivileged), running through ​Jun 15, 2026. Both ICs were added to the leadership nomination form; RVC tracking issues (RVC-773, 777) and Confluence CfC pages were created, and the announcement was sent to tech-announce. Nominate via the RISC-V Leadership Application form.

• ​Jun 1, 2026 Horizontal Committee elections OPENED — A combined Call for Candidates launched for Chair and Vice-Chair across all six RISC-V Horizontal Committees (Applications & Tools, ISA Infrastructure, Privileged Software, Security, SOC Infrastructure, Technology), running through ​Jun 15, 2026. The six HCs were added to the leadership nomination form; RVC tracking issues (RVC-743, 747, 752, 756, 763, 766) and Confluence CfC pages were created, and the announcement was sent to tech-announce. Nominate via the RISC-V Leadership Application form.

May   

• ​May 28, 2026 IME TG Internal Review LAUNCHED — Jose Moreira announced a two-week internal review of the Integrated Matrix Extension (Zvvm), running ​May 28, 2026 through ​Jun 11, 2026. The Zvvm family of Integrated Matrix extensions reuses the existing RISC-V “V” vector registers to represent matrix tiles, targeting microarchitectures from small in-order embedded cores to large out-of-order HPC/AI implementations. Spec PDF: riscv-unprivileged.pdf; source: riscv/integrated-matrix-extension; mailing list: tech-integrated-matrix-extension. Feedback via the mailing list or GitHub issues.

• ​May 28, 2026 Hot Chips 2026 — RISC-V Tutorial Announced — Hot Chips 2026 takes place August 23–25, 2026 at Memorial Auditorium, Stanford (Palo Alto, CA). Sunday August 23 features Tutorial 2: RISC-V, chaired by Marcel Tromp (Infineon), with four sessions: "Update on RISC-V standards and adoption, including profiles and platforms" (SiFive); "Evolution of enterprise open-source on RISC-V and architectural convergence on RVA23" (Canonical); "RISC-V profile and platform for interoperability with NVIDIA GPUs" (NVIDIA); "RISC-V for automotive: opportunities and challenges" (Infineon). Early registration closes July 31. Conference: hotchipssymposium.org · Registration: regfox.com/hot-chips-2026 · Advance program: hotchipssymposium.org/advance-program.

• ​May 26, 2026 Security Model TG Vice-chair Vacancy Election closed — 6 of 7 voters returned ballots. Andrew Dellow (Qualcomm) elected Vice-chair via Instant Runoff Voting with 5 first-choice votes (winning on round 2 after first-round elimination of Chang Liu, Xiaofei Gong, and Yudong Liu, all ISCAS, none receiving any votes). Other candidate: Luís Fiolhais (Individual), 1 vote. 0 exhausted ballots.

• ​May 26, 2026 🗳 CSC Requirements WG Vice-chair Vacancy Election closed — All 5 of 5 voters returned ballots. David Harris (Harvey Mudd College) elected Vice-chair with 5/0 (Plurality/FPTP/SNTV). Other candidate: Fei Zhang (ISCAS), 0 votes. 0 exhausted ballots.

• ​May 22, 2026 SPMP S-level Specification Public Review LAUNCHED — The 30-day public review for the RISC-V S-level Physical Memory Protection (SPMP) Specification opens today and runs through 21-Jun-2026. Spec source: github.com/riscv/riscv-spmp; companion isa-manual PR: riscv-isa-manual#2573; PDF: rv-spmp-spec.pdf. Feedback via mailing list tech-spmp@lists.riscv.org or GitHub issues on the spec repo. After the window, the Privileged ISA Committee will compile corrections and a public-review report ahead of recommending ratification.

• ​May 12, 2025 📣 AI Meeting Bots Disallowed in RISC-V Working Group Meetings — Compliance reminder issued to all chairs: third-party AI meeting bots (Otter.ai, Fireflies.ai, Sembly, Airgram, Beulr, Read.ai, Fathom, Oliv.ai, and similar) are not permitted in any Working Group, Task Group, SIG, Horizontal Committee, or governance meeting under the RISC-V International Association's Regulations, Appendix A — Intellectual Property Rights (IPR) Policy. Concerns cited: unauthorized disclosure of Contributions (§1.1), erosion of the Association's rights over Work Product (§§3.1–3.3), and patent/IP assertion exposure (§§2 and 6). Chairs are instructed to take the LFX host seat at every meeting and remove any bot — including personal note-taking assistants — before proceeding. Official LFX recording and identified human note-takers remain permitted. Questions: help@riscv.org.

• ​May 12, 2025 ✅ RQSC (RVS-3826) — Public Review Closed with No Feedback — The 30-day public review window for the RISC-V Quality of Service Controllers Table (RQSC) v0.9.2 Frozen Release ran from 2026-04-08 to 2026-05-08 across tech-prs, tech-announce, privileged-software, and isa-dev. No substantive comments were received (confirmed by Vasudevan Srinivasan on 2026-05-08). The spec is cleared to proceed through the remaining Ratification-Ready subtasks (Document Complete, Resolve Freeze Waivers, OS Enablement, Compliance) toward TSC Approval (~2026-05-29) and Board Ratification target 2026-06-25. [RVS-3826 · Frozen Release]

• ​May 12, 2025 ✅ SOC Infrastructure HC — 3 Trace Fast-Track Ratification Plans Approved — Three E-Trace family Fast-Track specs received SOC Infra HC Rat Plan approval, each with 7/7 Approve / 0 Object / 0 Abstain (unanimous, required majority exceeded). Specs are now cleared to move to Development under their ratification plans: (RVS-4549 Data Trace of Multi-memory Access & Compare-and-Swap; RVS-4600 Standard Support Packet Extension to E-trace; RVS-4454 Implicit Return Extension to E-Trace). All three are part of Iain Robertson's (Siemens) trace-spec stack under SOC Infra HC.

• ​May 6, 2026 🎉 Server Platform v1.0 — Ratified — The RISC-V Board of Directors approved the Ratification of the Server Platform Specification on 2026-05-06. Spec RVS-1781 transitioned from Specification in Publication to Specification Ratified. The v1.0 specification is published at github.com/riscv-non-isa/riscv-server-platform.

• ​May 6, 2025 🗳 Attached Matrix Extension (AME) TG — Chair + Vice-Chair Elections Concluded — 23 of 24 eligible ballots cast (one ballot added mid-vote after an eligibility correction). Chair: Zhong Su (Alibaba) elected with 16 votes vs Philipp Tomsich (VRULL) 6 (Plurality). Vice-Chair: Derek Hower (Qualcomm) elected via Instant-Runoff Voting (16 first-choice votes, 18 after Zhong Su elimination), defeating Philipp Tomsich (5) and Zhong Su (3). [RVG-135 · RVC-614]

• ​May 4, 2025 🆕 Logic Analyzer Trace TG — TSC PoW Approved — The TSC 2/3-majority vote concluded with 21 of 29 ballots cast (17 Approve / 0 Object / 4 Abstain); proposal of work approved. The new Task Group, proposed by Sajosh Janarthanan (Tenstorrent) under the SOC Infrastructure HC, will define an on-chip logic-analyzer trace specification. [RVG-971 · Vote results]

• ​May 4, 2025 🚀 Ziccid (RVS-3933) — TSC Approval to Send to Board for Ratification — The TSC majority vote concluded with 21 of 29 ballots cast; Approve is the winner. The Instruction/Data Coherence and Consistency Fast Track Extension is now sent to the Board of Directors for ratification. [RVS-3933 · Vote results]

April   

• ​Apr 30, 2026 ✅ IME TG Development Milestone Approved — The OpaVote on the Development Milestone of the Integrated Matrix Extension Specification concluded early with all 8 IME TG ballots returned (8 approve / 0 object / 0 abstain). The specification advances toward the next phase.

• ​Apr 28, 2026 ✅ RHTI Freeze Milestone Approved — The SOC Infrastructure HC Freeze Milestone Approval Vote for the RISC-V Hart Trace Interface (RHTI) Specification concluded with all 8 voting members returning ballots and the milestone approved.

• ​Apr 28, 2026 🔍 IOPMP ARC Review Resubmitted — The updated IOPMP specification was resubmitted to the ARC by Channing Tang (NVIDIA), incorporating feedback from the July 2025 ARC review and addressing the items recorded in subsequent ARC minutes.

• ​Apr 27, 2026 🗳 IME TG Development Milestone Vote Opened — OpaVote opened by RVI staff on behalf of the Integrated Matrix Extension Task Group for the Development Milestone Approval of the Integrated Matrix Extension Specification.

• ​Apr 27, 2026 🔍 Zibi Freeze ARC Review Submitted — Hou Junjie (ByteDance) submitted the Branch with Immediate (Zibi) Fast Track Extension for Freeze ARC Review. Internal Review completed with no comments requiring changes; ARC will review next, with a riscv-isa-manual HEAD PR requested.

• ​Apr 27, 2026 The Documentation Team has made all ratified specifications available in HTML online. This site will now serve as the central location for all ratified specifications to date and will continue to be updated with new specificatin ratifications moving forward.

• ​Apr 26, 2026 🏁 Version 0.11 of the Sail RISC-V Golden Model released — The highlight of this release is substantially improved performance on Linux boot.

  This release adds 13 new extensions; all mandatory extensions for RVA23U are now supported.

  Several configuration parameters have been added, along with new command line options.

  A binary release for the ARM macOS platform is available.

  The CI for the model now includes the recent release of the ACT 4.0.0 test suite.

  More details, including important bug fixes, are in the release notes at ​https://github.com/riscv/sail-riscv/blob/master/doc/ChangeLog.md#release-notes-for-version-011, and the release binaries are available at ​https://github.com/riscv/sail-riscv/releases.

• ​Apr 23, 2026 🏁 Graphics SIG — officially disbanded by TSC OpaVote — The TSC vote to disband the Graphics SIG concluded with 19 of 29 eligible ballots returned (quorum 15 met): 18 Approve / 0 Object / 1 Abstain, exceeding the 2/3 majority required. The SIG (RVG-6) had been inactive for 9+ months with no meetings since June 2025 and 3 voters on Probation. Archive activities (Jira, mailing list, GitHub repo, Confluence space) are now in progress. Prior CfC RVC-564 was cancelled without election.

• Submitted Froze​Apr 22, 2026n (v0.7) RVA23.1 and RVB23.1 Profiles Specifications to the Architectural Review Committee

• ​Apr 21, 2026 Long Instruction TG — recurring meetings established — Krste Asanovic (SiFive) and Stefan Wallentowitz (HM) have kicked off the Long Instruction TG coordination. Bi-weekly meetings will run on Thursdays at 8:00 PT / 17:00 CEST, starting 2026-05-07.

• ​Apr 17, 2026 📦 E-Trace Extensions — moving as a package to SOC Infra HC vote — The three E-Trace Fast-Track Extensions (Iain Robertson, Siemens) have completed review and are being taken forward as a single package for the SOC Infrastructure HC Governing Committee vote.

• ​Apr 20, 2026 Call for Candidates — Profiles SIG Vice-Chair — Deadline 2026-05-07. Candidate form via SurveyMonkey; details posted to tech-announce, tech-exchange, and sig-profiles. RVC-733.

• ​Apr 17, 2026 🗳 AME TG Chair & Vice-Chair CfC closed — CfC deadline 2026-04-07. Three candidates: Zhong Su (Alibaba), Philipp Tomsich (VRULL), Derek Hower (Qualcomm). Election added to the 2026-04-20 AME TG agenda. RVC-614.

• ​Apr 17, 2026 ✅ Ziccid (RVS-3933) — TSC Ratification Approval vote prepared — Vote text reviewed and approved by Andrew Waterman. RVS-3933 · Vote page.

• ​Apr 16, 2026 ACT 4.0.0 Release - ACT 4.0 is a major overhaul of the RISC-V Architecture Certification Test suite. The old riscof/riscv-ctg/riscv-isac/riscv-config flow has been replaced with an entirely new Python-based test compilation framework, a new testgen package for generating tests, and SystemVerilog-based functional coverage. The tests are now self-checking and many more RISC-V extensions are now supported. See the release notes for details.

• ​Apr 15, 2026 🗳 Dot-Product (Zvdot4a8i) Fast-Track — Plan Approved — Unprivileged IC Ratification Plan Approval Vote completed with all 8 ballots returned (8 Approve / 0 Object / 0 Abstain). Required majority of 5 exceeded. Spec RVS-1971 advances to Development. tech-unprivileged msg #1270.

• ​Apr 14, 2026 SmMTT TG Chair CfC opened — Call for Candidates for the SmMTT (Supervisor Domain Isolation) TG Chair position announced to tech-announce, tech-smmtt, and security mailing lists. Filling the vacancy left by Ravi Sahita. Candidate submission deadline: 2026-04-28. See RVC-679.

• ​Apr 13, 2026 TSC Charter Approvals — The Technical Steering Committee approved the charters for the Automotive SIG, Event Trace TG, and JITed & Dynamic Languages SIG with 22 ballots returned.

• ​Apr 13, 2026 🗳 RHTI Freeze Vote Opened — SOC Infrastructure HC freeze milestone approval vote submitted for the RISC-V Hart Trace Interface (RHTI) Specification.

• ​Apr 13, 2026 AME TG Extension — TSC IC members approved proceeding with the vote for a 1-year extension of the Attached Matrix Extension (AME) Task Group.

• ​Apr 9, 2026 ✅ RHTI TRCSTATE Ratification Plan Approved — SOC Infrastructure HC ratification plan approval vote for the RHTI TRCSTATE Fast Track Specification completed successfully.

• ​Apr 9, 2026 ✅ SPMP for Hypervisor Ratification Plan Approved — Privileged ISA Committee ratification plan approval vote for the SPMP for Hypervisor Fast Track Extension passed with all 5 ballots returned.

• ​Apr 9, 2026 📚 Ratified Specs HTML Library — Bill Traynor and Kersten are finalizing the publication of all ratified specifications in online HTML format, available for community review.

• ​Apr 8, 2026 🗳 TSC approved sending the Server Platform Specification to the Board of Directors for Ratification. Result: 16 Approve / 0 Object / 3 Abstain of 19 voters (required majority of 14 exceeded). Spec RVS-1781 transitioned to Specification in Publication.

• ​Apr 7, 2026 🗳 Privileged Software HC approved the Freeze Milestone for the RQSC Specification. Unanimous 4/0/0 vote (100% turnout). RQSC cleared to advance toward Ratification-Ready and Public Review. priv-sw msg #298

• ​Apr 1, 2026 🗳 Timing Fences TG 2026 Elections closed (8 of 9 ballots returned). Ronan Lashermes (Rambus) elected Chair (unanimous 8/0/0). Nils Wistoff (ETH Zurich) elected Vice-Chair via IRV. Term effective immediately through 2027-03-31. tech-timing-fences msg #160

• ​Apr 8, 2026 🎉 RQSC Public Review LAUNCHED — Vasudevan Srinivasan sent the public review announcement to tech-prs on Apr 8 16:52 PDT, opening the 30-day review window for the RISC-V Quality of Service Controllers Table (RQSC) Specification. Review is based on the 0.9.2 Frozen Release. Public Review milestone complete.

March

• ​Mar 17, 2026 📝 ARC Minutes for 3/11/2026 published. ARC completed review of the RQSC specification and approved it. Continued review of the Supervisor Domains specification with additional feedback to the authors.

• ​Mar 13, 2026 Call for Candidates for the Self-hosted Trace TG (Chair) issued. Submission deadline: March 27, 2026.

• ​Mar 13, 2026 Call for Candidates for the Attached Matrix Extension TG (Chair & Vice-Chair) issued. Submission deadline: March 27, 2026.

• ​Mar 6, 2026 📝 ARC Minutes for 2/25/2026 published. ARC spent the full meeting reviewing the CHERI specification and provided extensive feedback to the authors.

• ​Mar 2, 2026 Second Internal Review for CoVE-IO begins (March 1–16, 2026). The initial internal review took place two years ago; this fresh review precedes ARC review.

• ​Feb 27, 2026 📝 ARC Minutes for 2/11/2026 published. ARC approved PR 219 clarifying sstvala requirements in RVA supervisor profiles. CHERI TG advised that an additional PTE bit for capability revocation is acceptable.

• ​Mar 11, 2026 from ​@Bill Traynor​:

  • RISC-V International has released and published the following documents:

    • Volume I: Unprivileged Specification version 20260120: PDF, HTML 

    • Volume II: Privileged Specification version 20260120: PDF, HTML
      PDF downloads are also available from the right hand navigation of the HTML document.

      To report issues, please navigate to the GitHub repository for the manual and open an issue.

      More information for all published specifications can be found on the Technical Specifications page (link).

February

• ​Feb 27, 2026Several committees and groups finalized their leadership for the 2026–2027 term:

  • Certification Steering Committee (CSC): Bilal Zafar (Chair, 10xEngineers) and Ken Dockser (Vice-chair, Tenstorrent) were elected.

  • CHERI SIG: Alexander Richardson (Chair, Google) and Simon Moore (Vice-chair, University of Cambridge) were elected.

  • ACT SIG: Jordan Carlin (Vice-chair, Harvey Mudd College) was elected.

  • Academic & Training SIG: Paul Sherman was elected as Chair.

  • Self-hosted Trace TG: Iain Robertson and Bo Gan have agreed to serve as Chair and Vice-chair.

• ​Feb 26, 2026 RPMI v2.0 Ratification Plan Approved. The ratification plan for the RPMI Version 2.0 specification was unanimously approved by the Privileged Software HC, moving the spec forward in the ratification process.

• ​Feb 24, 2026 TSC Charters Approval. The Technical Steering Committee (TSC) approved the charters for four new technical groups: Instrumentation Trace TG, Server SOC II TG, Vector Matrix Extension (VME) TG, and the Space SIG.

• ​Feb 14, 2026 Version 0.10 of the Sail RISC-V Golden Model has been released, and is available at ​https://github.com/riscv/sail-riscv/releases.
  The highlight of this release is the switch to using the C++ backend of the Sail compiler. The generated model for the hart is wrapped in a C++ class, which opens up the possibility of instantiating multiple harts to simulate multicore platforms (though this is not yet implemented).

  A `--config-override` option has been added to specify one or more additional JSON configuration files that override the corresponding fields in a configuration. See the README for more information.

  This release adds 9 extensions and 2 unratified extensions.  The unratified extensions require the `--enable-experimental-extensions` option to be activated.

  More details, including updates to the configuration file and important bug fixes, are in the release notes at ​https://github.com/riscv/sail-riscv/blob/master/doc/ChangeLog.md#release-notes-for-version-010 .

• ​Feb 9, 2026 psABI TG Charter Approved. The TSC vote for the new psABI TG Charter concluded with a strong majority of 20 "Approve" votes.

• ​Feb 5, 2026 Server Platform Specification Frozen. The TSC approved the Freeze Milestone for the Server Platform Specification, clearing it to enter the Public Review phase.

• ​Feb 2, 2026 ARC Minutes for ​Jan 21, 2202 published. ARC approved RHTI Packet Formats to be pursed as a Fast-Track, assigned CSR numbers for the three direct CSRs defined in the Sspmp and Sspmpen (formerly Sspmpsw) extensions, and in the process changed the names of the sspmpswitch[h] CSRs to spmpen[h], and also Unprivileged and Privileged IC chairs declared an Official Release of Volumes I and II of the ISA manual.

• ​Feb 2, 2026 There’s a new approach to visualize our Technical Committees. It is simpler and more intuitive

  As it contains Chairs’ email, its access is internal-only, for RISC-V Members. It is behind GitHub, so you must be part of the https://github.com/orgs/riscv/teams/risc-v-members  to be able to see it (if you can’t reach out to help@riscv.org).

  You can access the Technical Committee Explorer here. Your feedback is more than welcome.

January

• ​Jan 30, 2026Several Calls for Candidates were issued for leadership positions (deadline Feb 14, 2026):

  • Server SoC II TG: Vice-Chair.

  • Performance Event Sampling TG: Chair & Vice-Chair.

  • Timing Fences TG: Chair & Vice-Chair.

  • Security Model TG: Chair & Vice-Chair.

  • CHERI TG: Chair & Vice-Chair.

  • Graphics SIG: Chair & Vice-Chair.

  • Datacenter SIG: Chair & Vice-Chair.

  • CHERI SIG: Chair & Vice-Chair.

  • UnifiedDB SIG: Vice-Chair.

• ​Jan 29, 2026UnifiedDB Project migrated to the main RISC-V Organization at GitHub: ttps://github.com/riscv/riscv-unified-db

• ​Jan 27, 2026 Internal review for RVA23.1 and RVB23.1 Profiles begins, ending 2026-02-11

• ​Jan 22, 2026RISC-V Technical Session | FeNN-DMA: A RISC-V SoC for SNN Acceleration on FPGA. ​Feb 19, 2026 7 a.m Pacific Time. RSVP here.

• ​Jan 21, 2026 Call for Candidates for the Certification Steering Committee Chair & Vice Chair is open and will end on ​Feb 4, 2026

• ​Jan 21, 2026 Call for Candidates (Vice-Chair) for Architectural Compatibility Test (ACT) SIG is open and will end on Feb 05 2026.

• ​Jan 20, 2026Internal Review for Branch with Immediate (Zibi) in progress. It will end on Feb 03 2026.

• ​Jan 20, 2026Internal Review for Integer Vector Absolute Difference (Zvabd) in progress. It will end on Feb 03 2026.

• ​Jan 19, 2026Internal Review for the Implicit Return Extension to the Enhanced Trace for RISC-V 2.0 (E-Trace) Specification in progress. It will end on Jan 23 2026.

• ​Jan 19, 2026Internal Review for the RISC-V Worlds in progress. It will end on ​Feb 2, 2026.

• ​Jan 15, 2026Dev Boards: Watching SpacemiT K3 and Tenstorrent Ascalon for RVA23 product releases. RISC-V Security safeguards and patches are landing for Spectre. Revy running on Allwinner v861).

• ​Jan 7, 2026 ARC Minutes for Dec 23 2025 published. At its 23 Dec 2025 meeting, ARC relaxed the AIA spec to allow non-32-bit device accesses as reserved with unspecified behavior for compatibility with real bus fabrics, reviewed the RQSC ACPI fast-track for follow-up feedback, and completed triage of all remaining ISA manual issues.

• ​Jan 6, 2026EcoSystem Lab Partners: 10xEngineers addressing bugs in github actions package, attempting to rebase commits. PLCT planning to add SpacemiT K3 to lab, expecting shipment in March. EPCC EPCC 25Q4 Lab Status Report, & Performance Tested SG2044.

2025

December

• ​Dec 22, 2025 Week in Review: This week centered on technical governance and specification maturity, marked by a strategic pivot in the Attached Matrix Extension (AME) framework to ensure architectural flexibility, deep technical debates on speculation barriers and trace correctness, steady progress on portable SIMD and custom extension context handling, and accelerating alignment on requirements and test artifacts for the 2026 certification roadmap.

• ​Dec 17, 2025Linux Plumbers Recordings are available here.

• ​Dec 16, 2025 ARC Minutes for

• ​Dec 12, 2025 Week in Review: this week centered on technical governance and specification maturity, marked by the recall of the AME data type vote to pivot toward a more flexible architectural framework, deep technical debate on speculation barriers and trace correctness, progress on portable SIMD and custom extension context handling, and accelerating alignment on requirements and test artifacts for 2026 certification.

• ​Dec 10, 2025Qualcomm acquires Ventana.

• ​Dec 10, 2025RISC-V Technical Session | RISC-V Technical Session | Labs, Containers and RISC-V. ​Dec 18, 2025, 7 a.m Pacific Time.

• ​Dec 10, 2025Call for Candidates for VME and RVM Profile closed this week. Vote starts soon.

• ​Dec 9, 2025 The Certification Steering Committee election for Community Member Representatives has concluded, with 8 ballots submitted out of 40 eligible voters, and using Instant Runoff Voting the two seats were awarded to David Harris (Harvey Mudd College) and Allen Baum (Individual Member), following a first-round tie and a second-round elimination of Mike Thompson (OpenHW Foundation).

• ​Dec 5, 2025 Week in Review: ACLIC–AIA alignment and cleanup toward internal review in fast-interrupts, deepening architectural debate on Smtw/Shtw timeout semantics in ARC, launching the first draft of a CX-agnostic context save/restore framework in the composable-extensions TG, and expanding engagement across RPMI and PQC cryptography as new contributors joined the ecosystem.

• ​Dec 4, 2025Election Results:

  • Space SIG: Chair: ​@Gianluca.Furano​, European Space Agency, Vice-Chair: ​@Fabrizio Magugliani​ , E4 Computer Engineering.

  • Profiles SIG: Chair: ​@Carl Perry (Unlicensed)​ , Individual.

  • Server SOC II TG: Chair: ​@Vedvyas Shanbhogue​ , Rivos.

  • Long Instruction TG: Chair: ​@Stefan Wallentowitz​ , Vice-Chair: ​@Krste Asanovic​, SiFive

  • Vector DSP TG: Chair ​@Dmitry Utyansky (Unlicensed)​ , Vice-Chair ​@Li Gaoshan​ , Xinsheng Technology.

• ​Dec 3, 2025HotChips presentations are available online.

• ​Dec 3, 2025CSC Updates: Over the past two weeks, CSC groups focused on resolving ambiguities in the ISA text, especially regarding when and how to add clarifying non-normative notes or supplemental context to normative rules, worked through cross-team questions on the ownership of specification changes, refined requirements and test-plan alignment, and continued routine governance activities including the CSC representative election.

  December 3, 2025 ARC Minutes for November 25, 2025 published: ARC proposed updates to the sPMP draft and shared it with the TG for what should be a final revision, while also resolving a vector SIG issue by updating the spec to cover double-precision register-pair handling for V/Zve64d with RV32_Zdinx.

  December 1, 2025 RISC V Technical Session | Programming RISC V Accelerators via Fortran. Video published.

November

• ​Nov 30, 2025 Week in Review: tightening FP64-in-RV32 semantics in the vector SIG, consolidating documentation-governance and charter feedback in the documentation SIG, deepening the security SIG’s analysis of multi-key memory-encryption threat models, driving functional-safety white-paper readiness and SoC-level PMC scoping, reviewing the proposed Smtw/Shtw extension in ARC, and delivering updated instruction naming in the P-extension TG while formally sunsetting the tech-config TG.

• ​Nov 26, 2025A refreshed draft of the Functional Safety SIG White Paper, featuring a new error-reporting chapter and relocating identified spec gaps to a companion document, is now open for final community review through ​Dec 26, 2025.

• ​Nov 25, 2025 The Automotive SIG has completed its elections, confirming Thomas Roecker (Infineon) as Chair and electing Sam Visalli (Tenstorrent) as Vice-chair for the new term.

• ​Nov 25, 2025 Call for Candidates for VME TG started. It will close on ​Dec 9, 2025.

• ​Nov 25, 2025 Call for Candidates for the RVM Profile TG started. It will close on ​Dec 8, 2025

• ​Nov 25, 2025 ARC Minutes for ​Nov 18, 2025 published: ARC advanced multiple items this cycle, including approving the renaming of Zvabd mnemonics, clarifying synchronization rules for xenvcfg.ADUE, refining the statement of RVWMO atomicity, directing a proposed E-trace update to proceed as a new fast-track extension, and formally approving the Zvdota and Zvbdota instruction families.

• ​Nov 22, 2025Instrumentation Trace TG finalized leadership election this week, confirming ​@Jay Gamoneda​ as chair and electing ​@Robert Chyla​ as vice-chair.

• ​Nov 22, 2025 Week in Review: This week working groups advanced several key threads: launching a scheduling survey for the new Attached Matrix Extension TC, iterating on a G-stage Dirty Log proposal for the RISC-V IOMMU (ping-pong buffers, sizing and event semantics) in the hypervisor/datacenter SIGs, debating trace back-pressure, trRamStopOnWrap behavior and the need for a global cross-triggering fabric in the debug/trace SIG, exploring how to validate VLEN-portable code and emulate intrinsics across implementations in the vector SIG, and kicking off focused review of the draft RVM23 profile’s mandatory vs optional extensions in tech-RVM.

• ​Nov 22, 2025 A survey is now available to determine the most suitable meeting time slot for the Attached Matrix Extension Technical Committee. All active participants are invited to submit their preferred option by November 30, 2025, using this link: https://www.surveymonkey.com/r/K2RCK3K.

• ​Nov 15, 2025 Week in Review: This week’s RISC-V ecosystem chatter spanned security-SIG scheduling alignment, segment-driven ISA requirement debates, documentation-template streamlining, vector-extension time-slot coordination, and governance updates including Performance Analysis SIG chair re-elections and the QoS SIG’s meeting-cadence kickoff.

• ​Nov 14, 2025High Assurance Crypto TG: the Vice-Chair election concluded confirming Roberto Avanzi as the new Vice-Chair.

• ​Nov 13, 2025The TSC’s OpaVote on the Unified Database TG Charter closed with 21 ballots cast, delivering a majority of 20 approvals, surpassing the required threshold and formally approving the UDB SIG charter. The SIG will be brought back to TSC in 6 months for an update on its progress (around May 2026).

• ​Nov 11, 2025 ARC Minutes for ​Nov 4, 2025 published. An updated SPMP spec and related fast-track extensions (including SPMP-for-Hypervisor, CFI shadow-stack items, Supervisor Domains, and a rewritten Ziccid proposal) were reviewed, with targeted restructuring, follow-on feedback, and a request for a ratification plan to align software PoCs and ecosystem readiness.

• ​Nov 10, 2025You can now run the RISC-V Sail model without installing Sail, Z3, or Opam, simply download the latest binary release from the riscv-sail-riscv repository and run it with no additional dependencies.

• ​Nov 7, 2025 Week in Review: This week’s RISC-V mailing list discussions centered on detailed review of the Ssgeien extension in the privileged spec, proposed standards for documentation and CSR formatting, and coordination around performance-modeling workflows.

• ​Nov 7, 2025 Ratification Plan unanimously approved (21–0–0) advancing RVA23.1 (RVS-4180) and RVB23.1 (RVS-4184) Fast Tracks, now actively in development.

• ​Nov 3, 2025 Heads-up on RISC-V Meetings and Encumbered Information.

• ​Nov 3, 2025 Call for Candidates for the Long Instruction TG is open. It will close on Nov 17th 2025.

October

• ​Oct 31, 2025Call for Candidates for the Vector Digital Signal Processing TG started. It will be open until ​Nov 14, 2025.

• ​Oct 31, 2025 Week in Review: Unified Database SIG discussed fixes to issues #730/#848 and regeneration of the profiles spreadsheet; Fast Interrupts TG discussed implementing late preemption and tail chaining in software; Attached Matrix Extension TG discussed data types, tile and accumulator shapes; ARC reviewed CHERI extension organization, Zvbc32e and Zvkgs specs, Server Platform, SPMP, and Supervisor Domains.

• ​Oct 30, 2202 ARC Minutes for ​Oct 2, 2025 published. The ARC engaged with the CHERI TG at the RISC-V Summit to refine CHERI extension organization, base ISA and naming considerations, advanced the Zvbc32e and Zvkgs specs toward approval, provided recommendations on Server Platform ISA behavior for thread/VM migration, and began reviewing the latest SPMP and Supervisor Domains drafts.

• ​Oct 30, 2025RISC-V Technical Session | Programming RISC-V accelerators via Fortran will be help on ​Nov 27, 2025, 7 a.m Pacific Time. Register here.

• ​Oct 29, 2025Call for Candidates for the Profiles SIG started. It will be open until ​Nov 12, 2025.

• ​Oct 29, 2025ARC Minutes for ​Oct 14, 2025 published. The ARC approved the Smpmpmt PMP-based Memory Types extension pending cosmetic edits, advanced the Zvzip fast-track with new nomenclature aligned to Packed SIMD P and scalar crypto, and green-lit the Zvfbfa and Zvfofp8min fast-track based on sufficient altfmt extensibility. The committee also queued SPMP for upcoming review and initiated evaluation of the Zvdota and Zvbdota dot-product fast-tracks, with continued analysis planned.

• ​Oct 29, 2025 ​https://www.youtube.com/watch?v=p5Je_FxIXts

• ​Oct 28, 2025 Week in Review: RISC-V Summit North America 2025, presentations attached to Sched. Some photos available here.

• ​Oct 28, 2025Call for Candidates for the Space SIG started. It will be open until ​Nov 10, 2025.

• ​Oct 28, 2025The Technical Steering Committee successfully concluded its vote to approve the updated RPMI TG Charter, with 19 ballots cast and an outcome of 18 approve, 1 abstain, and 0 objections, surpassing the required majority.

• ​Oct 18, 2025 Week in Review: Discussions centered on certification test coverage (CSC WG), hypervisor dirty-log tracking refinements and hardware-assisted PTE clearing, new fast-track proposals for S-mode memory protection and M-mode shadow stacks, coordination of crypto and security sessions ahead of the RISC-V Summit NA, and several TG meeting cancellations due to Summit preparations.

• ​Oct 17, 2025The Technical Steering Committee has officially approved the Crypto SIG Charter with unanimous support (19 votes in favor, 0 objections, 0 abstentions).

• ​Oct 16, 2025 Version 0.9 of the sail-riscv model has been released. Highlights include support for many new extensions (including the E base and BFloat16 extensions), PMA and memory map configuration, and a binary release of the simulator supporting other architectures. See the changelog for full release notes.

• ​Oct 14, 2025CSC-wide meeting minutes published; The meeting focused on reviewing and approving the Test Plan Working Group's charter, which was successfully approved with a quorum of 11 out of 13 voters present.

• ​Oct 14, 2025Call for Candidates | Vice-Chair, for the the High Assurance Cryptography Task Group has started and will close on ​Oct 28, 2025.

• ​Oct 14, 2025Leadership swap for the High Assurance Cryptography Task Group (​https://riscv.atlassian.net/browse/RVG-145). ​@Ruud Derwig (Unlicensed)​ from Synopsys is taking the Chair position, replacing ​@G. Richard Newell​, effective immediately.

• ​Oct 14, 2025The Call for Participation, Voters, and Observers for the Vector Digital Signal Processing TG has started and will close on ​Oct 28, 2025.

• ​Oct 13, 2025Mailing list for the Vector Digital Signal Processing TG is now available.

• ​Oct 13, 2025 Support for the Zvfbfwma extension has been added to the Sail model.

• ​Oct 9, 2025Call for Candidates for the Server SoC II is in progress and will end on ​Oct 23, 2025.

• ​Oct 9, 2025 Support for the Zvfbfmin extension has been added to the Sail model.

• ​Oct 9, 2025The JITed and Dynamic Languages SIG confirmed Martin Maas (Google) as Chair and Adam Zabrocki (NVIDIA) as Vice-Chair, following unanimous approval in the recent elections.

• ​Oct 7, 2025 Support for static PMAs has been added to the Sail model.

• ​Oct 7, 2025 The internal review period for the RISC-V Quality of Service Controllers Table (RQSC) ACPI Specification has started. The two-week review will end on ​Oct 21, 2025.

• ​Oct 6, 2025The Branch with Immediate Fast Track Extension got the approval from its Governing Committee (the Unprivileged ISA), for the Development Complete milestone.

• ​Oct 3, 2025 ARC Minutes for ​Sep 30, 2025 published: This week’s ARC activity included receipt of an updated CHERI specification, continued Supervisor Domains review including discussion of the optional Ssgeien extension, a resolution proposal on MSI PTE caching in the IOMMU specification, and the start of Zvfbfa/Zvfofp8min and Zvldot/Zvbdot fast-track reviews.

• ​Oct 3, 2025 Week in Review: mailing lists this week covered discussions on VME behavior, CSR access and mtime writability, CHERI profile governance, Datacenter persistence flush extensions, AI/ML scope definition, Server SoC planning, documentation tooling, debug process alignment, and matrix extension design feedback.

• ​Oct 3, 2025The vote on the Advanced Core-Local Interrupt Controller Spec concluded with 4 of 5 ballots cast; the majority threshold was not met (1 Approve, 3 Object), so the spec was not approved and will return to the authors and Privileged IC Chairs for revision.

• ​Oct 2, 2025TSC has started voting on the Crypto SIG Charter via OpaVote, running through October 16, 2025.

• ​Oct 2, 2025TSC has approved the Load-Acquire/Store-Release (Zalasr) Fast Track Extension (18–0–0), clearing it for submission to the Board for final ratification in October.

• ​Oct 1, 2025David Harris (Harvey Mudd College) was elected Chair and Adnan Hamid (Breker Verification Systems) Vice-Chair in the first CSC Test Plan Work Group elections.

September

• ​Sep 30, 2025 ARC Meeting Minutes for ​Sep 23, 2025 published. The ARC approved the Svukte extension, provided clarification guidance to the RPMI authors, engaged with the CHERI TG ahead of next month’s in-person meeting, initiated review of the Ziccid specification in consultation with the JITed and Dynamic Languages SIG, and continues steady review of the Supervisor Domains spec toward its next iteration.

• ​Sep 28, 2025 Support for the Zicfilp extension has been added to the Sail model.

• ​Sep 26, 2025 Week in Review: mailing lists this week included discussion on the Integrated Matrix Extension “Option G” figure generator (clarifications on “L (elements/VR)” and LMUL/widening) in tech-integrated-matrix-extension; an internal review/PR for the Hart-to-Trace Interface (RHTI) in sig-debug-trace-perf-mon and soc-infra; a proposed charter revision in sig-documentation; a BLIS retreat notice in sig-ml-ai-apps (cc: sig-hpc); a Summit NA flyer share in tech-ops-meeting; and membership updates in tech-vme.

• ​Sep 25, 2025 Vector Digital Signal Processing TG was approved by the BoD.

• ​Sep 24, 2025 ARC Meeting Minutes for ​Sep 16, 2025 published. Reviews continued on Supervisor Domains and the SPMP draft, Zvzip was deferred to 9/23, and ARC provided feedback to the Scalar Efficiency SIG on potential Fast Track candidates.

• ​Sep 24, 2025RISC-V Technical Session | Microarchitecture-Aware Custom RISC-V Instruction Design will be held on ​Oct 9, 2025. Register here.

• ​Sep 23, 2025Internal Review started for PMP-based Memory Types Fast Track Extension. It ends on ​Oct 8, 2025.

• ​Sep 23, 2025The PMP-based Memory Types Fast Track Extension completed its Development milestone.

• ​Sep 23, 2025The RQSC Table Specification completed its Development Complete milestone.

• ​Sep 22, 2025Call for Candidates for Automotive SIG started. It will end on ​Oct 6, 2025.

• ​Sep 22, 2025Concluding today, the AME Task Group approved (17–1, with 1 abstention) the proposed package of instructions, covering memory load/store, element-wise operations, and matrix-matrix multiplication, after a one-week OpaVote ballot, confirming broad support for advancing the Attached Matrix Extension (AME).

• ​Sep 19, 2025Call for Candidates for Instrumentation Trace started. It will end on ​Oct 3, 2025.

• ​Sep 19, 2025 Developer Board Program application forms added for Milk-V Megrez (limited availability), ESWIN EBC77, Banana Pi F3, Orange Pi RV2.

• ​Sep 19, 2025 Development Board Minutes for ​Sep 18, 2025Published. Watching Milk-V Titan launch for October 15th, expecting a board to be present at NA Summit Developer Zone. Reviews of BSD, Arch Linux, Gentoo, and Fedora-V Force.

• ​Sep 19, 2025 CSC Week in Review: discussions spanned TPWG charter finalization and governance on csc, certification test-plan mechanics on csc-test-plan (ECALL → JAL handlers, continue-on-failure, golden-model outputs), plus requirements and coordination updates on csc-requirements and csc-leads.

• ​Sep 19, 2025 Week in Review: mailing lists this week included discussions on VME accumulator counts, mtime writability and platform terminology, CHERI profile handling in governance, persistence flush extensions in Datacenter SIG, performance-events taxonomy and sampling, AI/ML scope in AME, tooling and DCO checks in Documentation/UnifiedDB, Server SoC agenda and planning, and matrixes for compliance and coverage.

• ​Sep 19, 2025 RVM Profile TG started its Call for Participation. It will end on ​Oct 3, 2025.

• ​Sep 17, 2025 ARC Minutes for ​Sep 9, 2025Published. Reviews continued on Smmpt and Supervisor Domains, ARC began assessing a new CHERI draft ahead of in-person discussions at the North American Summit, and feedback was provided on the improved Zvzip draft.

• ​Sep 16, 2025 ARC Minutes for ​Sep 2, 2025 Published. Supervisor Domains, IOPMP, and SPMP reviews continued this week, with ARC feedback focusing on reducing optionality in the IOPMP spec and suggesting some content be moved to a white paper.

• ​Sep 15, 2025CLIC has received Technical Committee approval, confirming specification development is complete. It now proceeds to Governing Committee approval. Once approved, the specification moves into stabilization.

• ​Sep 15, 2025Server Platform Specification is now Stable and moves into working on Freeze. Approval details available at ​https://riscv.atlassian.net/browse/RVS-4160 .

• ​Sep 12, 2025RISC-V Technical Session | TYRCA: A RISC-V Tightly-Coupled Accelerator For Code-Based Cryptography. Video available on YouTube.

• ​Sep 12, 2025 Week in Review: mailing lists this week included RHTI fast-track proposals, trace state handling, and spec versioning, fast-track requests for new addressing modes, and CSC requirements, test plan activities, RVCP operational definitions, and leadership coordination.

• ​Sep 10, 2025 TSC approved the Proposal of Work for the Vector Digital Sign TG. BoD approval is scheduled for ​Sep 25, 2025.

• ​Sep 9, 2025 TSC elections concluded. ​@Greg Favor (Unlicensed)​ elected Chair and ​@Philipp Tomsich​ elected Vice-Chair.

• ​Sep 9, 2025Event Trace TG elections concluded. ​@Bruce Ableidinger​ elected Chair and ​@Boris Shulman​ elected Vice-Chair.

• ​Sep 8, 2025 Spec Plan Editor update. Start From, Task Dependency and Three-Point Estimates added.

• ​Sep 8, 2025Public Review Period ended for Load-Acquire/Store-Release (Zalasr).

• ​Sep 5, 2025 Week in Review: mailing lists this week included discussions on VME accumulator counts, mtime writability and platform terminology, CHERI profile handling in governance, persistence flush extensions in Datacenter SIG, performance-events taxonomy and sampling, AI/ML scope in AME, tooling & DCO checks in Documentation/UnifiedDB, and Server SoC agenda/planning.

• ​Sep 5, 2025 All Disclosures are updated.

• ​Sep 4, 2025TSC Gap Analyses Published.

• ​Sep 3, 2025RISC-V Technical Session | Tensor Program Optimization for the RISC-V Vector Extension. Video available on YouTube.

• ​Sep 3, 2025The RVA23.1 and RVB23.1 profiles were admitted to follow the fast track process. Both are now under Planning.

• ​Sep 3, 2025 ARC Meeting Minutes for 2025-08-26 Published. The ARC clarified that MPTE/MTE bit updates in the tcontrol CSR by the Snrnmi extension are invisible to M-mode debugging (to be noted non-normatively in the spec), approved fast-track RVA23.1/RVB23.1 with Ssctr guidance, continued SPMP and Supervisor Domains reviews, and recommended CTR/Svadu as optional and Zkr as mandatory in the draft Server Platform spec.

• ​Sep 3, 2025Internal Review period for RISC-V Internal Review: Zvfbfa and Zvfofp8min, Zvldot and Zvbo, and Ziccid ended without any feedback. Specifications move to Freeze.

• ​Sep 3, 2025libiopmp v0.1.0 was released under the IOPMP TG GitHub repo, an extensible driver supporting the latest IOPMP spec v0.8, multiple models/configurations, and reference programs for easy testing and feedback.

• ​Sep 3, 2025 The Smpmpmt Fast Track extension has been approved for the Ratification Plan milestone.

• ​Sep 3, 2025 The Integer Vector Absolute Difference Extension has been approved for the Ratification Plan milestone. 

• ​Sep 2, 2025 IOPMP Specification update: alignment on simplifying the IOPMP spec by keeping a streamlined core in the standard while moving complex options and guidance into application notes, with ​@Channing Tang​ and ​@Paul Ku​ leading the review and ARC engaged for iterative feedback.

• ​Sep 1, 2025 Next RISC-V Technical Session published: TYRCA: A RISC-V Tightly-Coupled Accelerator For Code-Based Cryptography. ​Sep 11, 2025, 7 a.m Pacific Time.

• ​Sep 1, 2025 Call for Participants, Voters and Observers for Long Instruction TG ended.

• ​Sep 1, 2025 psABI elections concluded: ​@Kito Cheng​ elected Chair and ​@Jessica Clarke​ elected Vice-Chair.

• ​Sep 1, 2025 Sail Development Highlights

  • Support for the RV32E and RV64E base ISAs has been added.

  • Support for the Zihintntl and Zihintpause extensions has been added.

• ​Sep 1, 2025 Call for Participation for the Instrumentation Trace started.

August

• ​Aug 29, 2025Attached Matrix Extension TG have defined the date for its extra meetings, it will on 10PM GMT+8, Sept 3 (Wednesday) | 7AM PDT, Sept 3 (Wednesday). It will show up at ​https://tech.riscv.org/calendar. Reach out to ​@Siqi Zhao​ if need be.

• ​Aug 28, 2025ARC Meeting Minutes Published. The ARC continued reviews on CHERI, Supervisor Domains, SPMP, and IOPMP, clarified questions on Zihintitl/Zca and menvcfg behavior, and admitted Zvzip as a fast-track extension candidate.

• ​Aug 28, 2025 ​@Ken Dockser​ reported that the the Governance Committee clarified the meeting attendance conundrum:

  • All scheduled meetings count (unless cancelled ahead of time), even if quorum isn’t reached.

    • If you attend, you get credit.

    • If you don’t attend, it counts against you.

• ​Aug 28, 2025 PTE Reserved-for-Software Bits 60-59 Fast Track ISA,
  PTE Reserved-for-Software Bits 60-59 Fast Track IOMMU and
  Boot and Runtime Services (BRS) were Ratified by the Board of Directors

• ​Aug 28, 2025 RVM TG and Instrumentation Trace TG were approved by the Board of Directors.

• ​Aug 27, 2025 Crypto SIG elections concluded: ​@Markku-Juhani Saarinen​ elected Chair, ​@Nicolas Brunie​ elected Vice-Chair.

• ​Aug 26, 2025 Meeting Disclosures in Chinese are now available here.

• ​Aug 26, 2025 RISC-V Tech Journal was created.