RISC-V Community:

Privileged Horizontal Committee

Source:

riscv/riscv-isa-manual

20250508

HTML, PDF

20240411

HTML, PDF

20211203

PDF

1.11

PDF

1.10

PDF

1.9

PDF

1.7

PDF

PTE Reserved-for-Software Bits 60-59

PDF | Source

Svrsw60t59b

The RISC-V Debug Specification

PDF | Source

Sdext, Sdtrig

RISC-V Advanced Interrupt Architecture

PDF | Source

Smaia, Ssaia

RISC-V Control Transfer Records

PDF | Source

Smctr, Ssctr

RISC-V Pointer Masking

PDF | Source

Smmpm, Smnpm, Ssnpm, Supm, Sspm

The RISC-V Instruction Set Manual Volume II: Privileged Architecture (Priv 1.13) 

PDF

Sm1p13, Ss1p13

Double Trap

PDF | Source

Ssdbltrp, Smdbltrp

RISC-V Quality-of-Service (QoS) Identifiers

PDF | Source

Ssqosid

Obviating Memory-Management Instructions after Marking PTEs Valid

PDF | Source

Svvptc

Resumable Non-Maskable Interrupts

PDF

Smrnmi

RISC-V Supervisor Counter Delegation

PDF | Source

Smcdeleg, Ssccfg

RISC-V Indirect CSR Access (Smcsrind/Sscsrind)

PDF | Source

Smcsrind, Sscsrind

Hardware Updating of PTE A/D Bits (Svadu)

PDF | Source

Svadu

RISC-V Cycle and Instret Privilege Mode Filtering (Smcntrpmf)

PDF | Source

Smcntrpmf

RISC-V Advanced Interrupt Architecture

PDF | Source

Smaia, Ssaia

PMP Enhancements for memory access and execution prevention on Machine mode (Smepmp)

PDF

Smepmp

RISC-V Privileged Architecture 1.12

PDF

Sm1p12, Ss1p12, Sv57, Hypervisor, Svinval, Svnapot, Svpbmt

RISC-V Count Overflow and Mode-Based Filtering Extension

PDF | Source

Sscofpmf

RISC-V State Enable Extension

PDF | Source

Smstateen

RISC-V "stimecmp / vstimecmp" Extension

PDF | Source

Sstc