The RISC-V Supervisor Binary Interface, allows supervisor-mode (S-mode or VS-mode) software to be portable across all RISC-V implementations by defining an abstraction for platform (or hypervisor) specific functionality. The design of the SBI follows the general RISC-V philosophy of having a small core along with a set of optional modular extensions.

Version 3.0 adds PMU event information and base event type; new extensions for MPXY, DBTR, FWFT, and SSE; additional error codes; and clarifications in the set_timer function and IPI and RFENCE error codes.

Version 2.0 added a debug console, system suspend, nested acceleration, steal-time accounting, PMU snapshot, and various error codes; relaxed counter width requirements on PMU firmware counters; reserved space for firmware events; and clarified several extensions.

Latest version: 3.0 Date: July 2025

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All published versions of the specification are listed below from newest to oldest.