About

• Version: 1.4

• Creation date: 2022-04-22

• One line description: What must be complete before TSC can approve a specification for ratification

• Author(s): Mark I Himelstein, Stephano Cetola

Definitions

Milestones

See the Specification Development section of the RISC-V Development Process documentation for more milestone information.

Tasks

Milestone criteria are defined in the Jira for the RISC-V Specification Lifecyle project. Each specification has a main Jira task which includes a set of sub-tasks for each milestone. Each sub-task contains detailed information about the criteria.

When the Jira tasks don’t directly apply, such as a new specification type, the minimum tasks defined should be used as a reference.

Background

This document acts as a minimum viable definition of tasks, while the Jira contains the details. For any given specification, see the relevant Jira sub-task for how the specification meets the requirements defined in this process.

Details

The specification owner must complete or provide waivers for all of the List of Tasks to reach the given milestone. The TG must maintain and keep Jira up to date by:

1. Providing milestone date projections and a monthly status updates in the Ratification Plan

2. Updating the Jira sub-tasks with relevant information such as links to completed work

3. Identifying any delays and providing mitigation plans

List of Tasks

Freeze

1. Document Complete - the document must describe the semantics of instructions or operations and any other extension-specific visible state.

2. Opcode Support - there must be enough opcode support for GCC to be functional but not optimized.

3. Simulators - There must be enough simulator support so that basic RISC-V tests can be run. See Architectural Compatibility Test for more details.

4. Application Binary Interface - All applicable ABIs must be updated as relevant and changes must be discussed during architecture review

5. Compiler Support - Support GCC and LLVM without optimizations.

6. Architecture Compatibility Tests (ACT) - Create tests and test input. See the Architectural Compatibility Test for details.

7. Sail Golden Model - Work with RISC-V staff to update the Sail Golden Model as appropriate.

8. Architecture Review - See the Architecture Review Policy for details (currently in development).

9. Proof of Concept (POC) - Propose POCs to the governing committees for approval, or approve the waiver of PoC at the governing committee’s discretion. The TSC must be informed of this waiver and may reject the waiver. The committee may ask for revisions in the POC.

10. RISC-V Publication Policies - Abide by other pertinent policies and process (e.g. encumbered information, friendly terminology, anonymous contributor) currently in development.

Ratification Ready

1. Resolve Freeze Waivers - Either resolve freeze waivers or get new waivers for vote-ready updating the status of the old waivers.

2. Document Complete - Complete updates to the specification based on review comments.

3. Architecture Review - See the Architecture Review Policy currently in development. This step is only required if substantive changes were made after public review.

4. Unified Discovery - We are waiting on Unified Discovery specification to be ratified. A standing waiver will be used for specifications developed before then.

5. Regression Testing - Identify and test interactions with previously ratified specifications.

6. Architecture Compatibility Tests (ACT) - All tests and inputs should be updated with any changes since public review.

7. Industry Standard Tests - Generate correct test results from any appropriate industry-available license-friendly tests (e.g. IBM floating point tests, AES tests, etc).

8. OS Enablement - See the document for details, currently in development.

9. RISC-V Profiles - The extension(s) must be included in at least 1 RISC-V profile.

10. RISC-V Publication Policies - Abide by other pertinent policies and processes (e.g. encumbered information, friendly terminology, anonymous contributor) currently in development.

Waivers

The current RISC-V Policies and Procedures does not allow for waivers. All existing waivers will continue until no longer valid. New waivers will not be created.

If a waiver is needed, a request should be sent to the TSC chairs and the RISC-V VP of Technology explaining the need.

Exceptions

The RISC-V VP of Technology is the escalation path for all process issues, with the authority to resolve them or, if necessary, escalate further to the TSC or the BOD.

Version History