2025-12-10 TSC Overflow Meeting
Date
Dec 10, 2025
Disclosures
Participants
Agenda
Slides: link
Justification pages: link
Presentations
Votes
None
Notes & Action Items
Meeting recording and transcript: link
Meeting Summary
New PoW: Logic Analyzer Trace Task Group
The discussion focused on a proposal for a standardized Logic Analyzer Task Group proposal to improve post-silicon debug capabilities. Sajosh presented the need for this standardization, highlighting that current debug methods only capture a snapshot of system failures, far removed from the actual point of deviation. The proposed logic analyzer control block aims to move data collection closer to the point of failure, enabling better observability and performance monitoring. The task group will define packet formats for both E-trace and N-trace, as well as the logic analyzer control, while collaborating with software vendors to develop a common software stack. Security concerns were discussed, with Robert noting that debug and trace capabilities can be disabled or secured through JTAG. Greg suggested standardizing the format for expressing signal information to facilitate tooling and EDA software development.
The team discussed publishing the format for event-action pair registers, which will support both combinator logic conditions and sequential conditions, and agreed to proceed to broader member review after making some updates.
Continuation: Updated RISC-V Policies
Ken presented updates to the RISC-V Policies, clarifying that contributions made in meetings are subject to the RISC-V IPR policy, and explained the voting requirements for TSC members, including the 50% participation threshold and probation process.
The meeting focused on discussing a new policy that requires TSC members to maintain a 50% participation rate, with probation starting April 1st for those falling below this threshold after January 1st. Ken clarified that probation means members are not eligible voters and do not affect quorum or vote outcomes, though they can still vote while on probation. Greg and Guy raised concerns about the policy's loopholes, particularly how members could continuously participate in just one event per month while remaining below 50%, and suggested adding a time requirement to get back above 50%. Ken acknowledged these concerns and noted that the board intentionally chose not to make the policy more stringent, preferring to encourage participation rather than create additional barriers.
The continued discussion focused on clarifying technical committee participation policies and procedures. Ken explained changes to voting participant opt-in requirements and clarified that both voting and non-voting participation statuses require explicit opt-in, with non-participation being the default. The group reviewed meeting types and leadership structures, with no significant changes from previous policies.
Task Group Extension Justification
Rafael presented a list of 13 task groups that have exceeded their 2-year completion timeline, explaining a two-step approval process for extensions: first from the governing committee, then from the TSC. The chairs and vice-chairs were invited to provide context and justification for their groups' extensions, with 12 responses received so far, while the secret model group's input was still pending.
The CoVE-IO Task Group (TG) presented their request for a one-year extension to the TSC, with Samuel explaining they need time to update the specification to version 0.3 and conduct new internal reviews. Greg clarified that while the governing committee must first approve the extension, the TSC holds final decision-making authority. The TG acknowledged resource constraints, particularly for building the POC, and was asked to provide a detailed plan with timelines for completing the remaining work and meeting the freeze milestone checklist. The task group discussed the need to update their ratification plan to reflect delays in TG progress and align with new policies. Samuel estimated version 0.3's release for early 2026.
Rich reported that the P Extension specification was being finalized, with most deliverables completed except for Linux task switching code and intrinsic function updates. The group agreed to prepare an updated, fully resourced ratification plan for governing committee approval, with a target to return to the TSC by February.
The CHERI focused on reviewing the status and progress of various task groups and specifications. Alex reported on the stable state of the spec, which has been clarified for vendor extensions, and the need to update freeze items with final opcode and CSI allocation. Greg suggested creating a new plan after estimating the completion of the ARC review.
Rafael discussed the need to sync with Ravi regarding the CoVE and CoVE-IO progress and the importance of putting together a new RAT plan.
Krste mentioned the progress of SMMTT, emphasizing the need for resources to finish the pieces.
Paul reported on the status of the IOPMP spec, awaiting new feedback, and Greg suggested working with the TPMs to create an updated timeline.
Eudora highlighted the ongoing discussions for AME, targeting the completion of the first part of the spec by the end of the year.
Markku-Juhani proposed rechartering a task group for post-quantum cryptography, considering the architectural demands of the instruction.
The conversation ended with a discussion on the process for rechartering and the potential involvement of the Security HC.
Detailed Minutes
New PoW: Logic Analyzer Trace Task Group
Multiple contributors. Thanks to all!
Motivation: Current data collection modes can be a long way from the failure point.
Discussion:
What value will this have for software?
The data can enhance the Performance Counters which will provide some standard support in the software stack. It will also be helpful to EDA software.How will the signal names be made available as a part of this design?
Based on the fact the primary use is for hardware debug, this does not need to be shared outside of a company with the current design.Does this provide a new attack space for side-channel attacks?
Secure JTAG and other known techniques will apply.Why standardize in RISC-V?
Wanted to build on existing RISC-V ecosystem. DPTM SIG discussed this and felt that the reuse of the existing trace structure would work well.Will you publish how triggers and actions will work?
Yes it will be part of the specification.AI: Some updates to PoW were suggested to be able to clarify what can be standardized.
Approval granted by TSC Chair to proceed to Member Review with the previous updates.
Continuation: Updated RISC-V Policies
Clarifications from previous discussion
Contributions allowed to be corrected, but may not pulled back.
This is driven by the RISC-V IPR Policy (Intellectual Property Rights).
It applies to all disclosure, not just those which are used.
See the RISC-V Regulations for more details (link).
Clarified that HCs and ICs were both governing committees
Participating and Voting Requirements
Sliding window of 3 months.
This will start accrual on January 1.
Voters on probation do not count toward majority.
Non-TSC Participation
Voting rights granted immediately, unless you’re on probation
Members must Opt In to be Participants – Voting or non-voting.
New changes:
Ad Hoc committees added for technical committees
TGs may include related collateral
Project Manager has been dropped.
Additional questions/discussion:
Will post new slides (link)
New policy is in wiki (link)
Please see them
Task Group Extension Justification
Background
New policy requires work complete in 2 years and if not, an extension must be requested.
Approvals extensions will go back to GCs for approval and then to TSC
Need to add questions about having needed resources and timeline for completing ratification.
Group Details:
CoVE-IO:
Resources at risk. Expect to update spec in January and work toward freeze then.
Need to update the Ratification Plan schedule.
AI: Please make updates and return in February TSC meeting.
Packed SIMD:
Conversion to Asciidoc underway
Only Linux PoC code remains TBD. All other software covered.
Intrinsic re-work also needed.
No resource needs.
Challenges exist (see content for details) – ARC, Vector DSP, State Enable
AI: Updated schedule
CHERI:
Spec stable. Awaiting final Op Code and CSR allocation.
Generally following the original plan. Will re-work plan.
SPMP, CoVE, CLIC, AME:
No chairs, but will follow-up on the resources and new plan schedule.