2025-04-02 Official Meeting Notes

2025-04-02 Official Meeting Notes

Date

Apr 2, 2025

Disclosures

RVI_Disclosures_Female_Short.mp4

Participants

Voters | Quorum Required - 16

Name

Affiliation

Voting Member

Attended

Join Time

Leave Time

Name

Affiliation

Voting Member

Attended

Join Time

Leave Time

1

Allen Baum - ISA Infra HC Vice-chair

Esperanto

X

X

10:09 AM

12:02 PM

2

Austin (Jianlin) Gao

Tencent

X

 

 

 

3

Avi Timor

Google

X

X

10:05 AM

11:20 AM

4

Charlie Su

Andes

X

X

10:04 AM

12:02 PM

5

David Brash

Rivos Inc.

X

10:04 AM

12:02 PM

6

David Chen

Stream Computing

X

 

 

 

7

David Weaver

Akeana

X

X

10:00 AM

12:02 PM

8

Earl Killian - Unpriv IC

Aril Inc.

X

X

10:07 AM

12:02 PM

9

Erich Focht

Openchip

X

10:05 AM

12:02 PM

10

Frans Sijstermans

Nvidia

X

X

10:09 AM

12:02 PM

11

Greg Favor - TSC Chair

Ventana Micro Systems

X

10:03 AM

12:02 PM

12

Guido Costa Souza

Brazilian Ministry of Science

X

 

 

 

13

Guy Lemieux - Com/Individ Elected Rep

Individual

X

10:02 AM

12:02 PM

14

Haibin Shen

Chengwei Captial

X

 

 

 

15

Jian Zhang

Beijing Institute of Open Source Chip

X

X

10:01 AM

12:02 PM

16

John Hengeveld

Intel

X

 

 

 

17

John Leidel - Technology HC Chair

Tactical Computing Labs

X

 

 

 

18

Kan Shi

ICT CAS

X

 

 

 

19

Ken Dockser - Strategic Elected Rep

Tenstorrent

X

X
(partial) 

10:14 AM

11:00 AM

20

Manu Gulati

Qualcomm

X

10:03 AM

12:02 PM

21

Paul Holt

Synopsys

X

X

10:10 AM

12:02 PM

22

Peter Chun

Huawei

X

 

 

 

23

Philipp Tomsich - TSC Vice-chair

VRULL

X

X
(partial)

10:01 AM

11:00 AM

24

Roger Espasa - Strategic Elected Rep

Semidynamics

X

 

 

 

25

Shi Yijun

Sanechips/ZTE

X

 

 

 

26

Shubu Mukherjee (Krste)

SiFive

X

10:00 AM

11:57 AM

27

Siqi Zhao

Alibaba Cloud

X

 

 

 

28

Tom Zhao

Phytium

X

 

 

 

29

Wei Wu

ISCAS

X

X

10:01 AM

12:02 PM

30

Zhangzi Tan

RIOS

X

 

 

 

Non-Voters

Name

Affiliation

Attended

Name

Affiliation

Attended

Andrea Gallo

RISC-V

X

Anup Patel - Priv SW HC Chair

Ventana Micro Systems

 

Andrew Dellow - Security HC Chair

Qualcomm

Andrew Waterman - Priv IC Vice-chair

SiFive

 

Greg Sterling

RISC-V

Jeff Scheel

RISC-V

X

Krste Ansanovic

SiFive

X

Rafael Sene

RISC-V

X

Ravi Sahita - Security HC Vice-chair

Rivos Inc.

X

Ved Shanbhogue - SOC Infra HC Chair

Rivos Inc.

 

Bill Traynor

RISC-V

X

Sun Hao

Alibaba

X

Kito Cheng

SiFive

X

Carl Perry

Individual

X

Ana Pazos

Qualcomm

X

Agenda

Approval of March 5, 2025 Meeting Minutes (link) - 3 min

(PoW Second Review) https://riscv.atlassian.net/wiki/spaces/TOXX/pages/276135937 (see Persistent Memory Updates presentation in the presentation table below)(Hao Sun, Alibaba) - 15 min
(New PoW) https://riscv.atlassian.net/wiki/spaces/PXXX/pages/294158386 (Kito Cheng, SiFive - Ana Pazos, Qualcomm - Christoph Müllner, VRULL) - 15 min
(New PoW) https://riscv.atlassian.net/wiki/spaces/TOXX/pages/370507777 (Andrea, Rafael, Carl) - 15 min
Scalable TEE for Workloads on RISC-V platforms Whitepaper review (email link) (Andy, Ravi, Andrea) - 10 min
Unified Discovery TG Challenge (Andrea, Philipp) - 10 min

Presentations

Title

Presenter

File

Title

Presenter

File

1

Persistent Memory Updates

Hao Sun, Alibaba

 

2

Processor Core Specification level Proposal

David Weaver, Akean

 

3

psABI Proposal

Kito Cheng

 

Votes

Quorum Status:
Vote Record

  • Agenda Item or Motion:

    Approve March 5, 2025 Meeting Minutes (link)

  • Motion Made By: David Weaver

  • Motion Seconded By: Manu Gulati

Voting Results:

  • In Favor: 17

  • Opposed: 0

  • Abstentions: 0

Outcome: Motion Passed

Additional Notes: Approved at 0:12 mark in meeting

Notes & Action Items

Recording: Video Conferencing, Web Conferencing, Webinars, Screen Sharing

Action Items

Update Persistent Memory Proposal for Work with the discussion feedback and then email the TSC with updates per minutes (@sun hao)
Update Developer Relations SIG proposal with updates per the review and return to TSC (@Rafael Sene , @Carl Perry )
Re-start the TSC discussion thread on “Processor Core” to prompt feedback (@David Weaver )
Schedule the overflow meeting for the whitepaper review and Unified Discovery discussion (@Jeff Scheel )

Summary

Jeff opens the RISC-V TSC meeting and welcomes attendees. Philipp mentions that Suchi won't be joining but provided an update. Jeff takes attendance and works on achieving quorum. He plays the standard disclosures video, addressing community guidelines, antitrust policies, and export controls. After some technical difficulties, the group eventually reaches quorum. The meeting minutes from March 5th are approved, and the group moves on to discuss a proposal from the persistent memory team, with Sun from Alibaba leading the presentation.

Persistent Memory Application TG Proposal for Work Update

The meeting focused on defining the scope and objectives of a task group aimed at resolving issues related to memory persistency. The group discussed the need for a clear definition of what persistency means, with some members suggesting that it should be defined in terms of use cases. There was also a discussion on the need for a point of persistency and instructions to ensure that data is pushed out to that point. The group also discussed the importance of defining the property of non-volatility and how it can be achieved. However, there was a lack of clarity on what the task group is trying to achieve, with some members suggesting that the charter needs to be more specific. The conversation ended with a consensus that the use case definition is important and needs to be better defined.

psABI Task Group Proposal for Work Review

The TSC discusses reforming the psABI Task Group to create version 2.0 of the psABI specification. Kito presents the proposal, explaining that the group aims to incorporate new features developed since version 1.0, including CFI-related features, vector calling conventions, and C23 language standard updates. The group will also continue to help other test groups identify ABI issues and serve as a neutral forum for ABI discussions. Allen raises a question about whether this should be an ongoing SIG rather than a task group, but Philipp clarifies that the group is producing a work product specification.

The group discusses the formation of a task group for PSA (Processor-Specific Application Binary Interface) 2.0. They clarify that ongoing maintenance should remain with the Tool Chain SIG, while the new task group will focus on producing the 2.0 work product. The scope of the task group is debated, with concerns about how to handle minor updates and new extensions. They decide to give an action item to the governing committee to propose a process for handling ongoing API updates. The group agrees to allow the proposal to proceed to broader review, with some clarifications needed on the scope and maintenance responsibilities. They also discuss the need for a clear process for addressing new extensions and API updates without creating a new major version each time.

Developer Relations SIG Proposal for Work Review

Rafael presented a proposal for a developer relations program to improve the presence of Risk 5 on the web and enhance the developer experience. The program aims to create a unified and centralized way to handle developer needs, increase Risk 5 visibility, and empower developers to adopt Risk 5 quickly. The proposal includes establishing a structured developer relations framework, managing a communication platform, and identifying gaps. The program will initially leverage existing resources and may require a dedicated staff member. The proposal was well-received, but there were concerns about the structure and governance of the program. The TSC was suggested as the governing committee, but the possibility of creating a new committee was also discussed. The proposal will be taken offline for further discussion with the marketing team.

Processor Core Specification Proposal

The Technical Steering Committee discusses a proposal for a new intermediate level of specification called "processor core" that would sit between ISA profiles and platform specifications. David Weaver presents the concept, explaining it would include ISA profiles as well as partial ISA features like debug, trace and interrupt control. The committee debates the relationships between profiles, processor cores, and verticals, with some suggesting it should be a many-to-many relationship. They discuss how to organize and limit the combinations to manage complexity. The group agrees to continue the discussion via email and potentially in an overflow meeting next week.

Wrap-up

They also plan to review a trusted execution environment white paper at the overflow meeting.

Detailed Notes

  • Persistent Memory Application TG Proposal for Work Update

    • Discussion:

      • Are there PMA impacts such that we might want to define “persistent memory regions”?
        Answer: Undecided at this time. Platform may have difficulty handling.

      • Would the new instructions would need to ensure that persistency has occurred?
        Answer: We need completion semantics as well as ordering semantics.

      • The proposal has not defined “persistency”. It sounds like the definition is that a memory store is readable after power cycle directly from processor.

      • Definition of persistency should start with the use-case and the mechanism used to deliver it.

      • Issues which need to addressed before we start the group:

        1. Define the persistence.

        2. Detail the one or more use cases (or solutions) and the requirements to solve them.

      • Recommend posting to an update proposal which address issues to the TSC mailing list when ready and decision to proceed asynchronously could (@sun hao won’t be able to reply if this is under TSC mailing list, so RVI Staff will help).

  • psABI TG Proposal for Work Review

    • Because this sounds like it’s long running, should it be a SIG?
      Answer: the work product (specification) cannot be delivered via a SIG. The Toolchain SIG has been informally maintaining the psABI document, but now need a TG to build 2.0 version of the document.

    • Do folks who need content for 2.0 know where to go?
      Answer: the task group will serve that role while in existence but will still work with Toolchain SIG.

    • Action Item: Toolchain SIG should keep the maintenance responsibility of the psABI document.

    • Action Item: Apps & Tools HC needs to address how to handle regular update items like new ELF Flags.

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