TSC Strategic Priorities Meeting

Date

Jun 11, 2025 Jul 9, 2025 Aug 6, 2025

Disclosures

RISC-V Disclosures Video

Open

Participants

Agenda

• Premier Members GapsPreview

• Strategic Members GapsPreview

• Community Organization and Community IndividualsPreview

Presentations

Votes

None

Notes & Action Items

Audio links:

• June 11: link

• July 9: link

• August 6 (second hour): link

Detailed Notes

• Next TSC Meeting: Platform SIG Needs Discussion (Andrea, Greg) (10 Minutes)

• Background for meeting:

  • The goal is alignment within RISC-V

  • Participation is important

  • Resources are limited, thus let’s focus on items we can achieve within the next year

  • Collaboration makes us all more efficient and improves ROI

• Premier Member Gaps Discussion

  • ISA

    • Virtualization for Real-time Processors noted as important to Automotive – BOSC, SiFive, Infineon, Synopsys, and others…

    • Enterprise/Datacenter/… gaps (#3)

      • Needs to be split in multiple pieces

      • Will focus on ISA items more than non-ISA

    • Vector item (#5) has new item of 56x56 carry-save-multi-add.

    • Speculation barriers being worked

    • Scalar (#7)

      • Most being worked starting with SIG, but also includes proposed Long Instruction TG

    • Sail (#8) wants Sail to move faster.

    • Long Instruction (#9) supported by Akeana as well.

    • Atomic Enqueue (#10) newly raised to mailing lists. Support being posted to list would be beneficial.

    • Vector Extension (#11)

      • crcfolder and vgmulxor instructions apply to storage. No need for Storage SIG at this time but will explore. Note: Carryless multiply helps here too.

      • fp4 not yet being looked at in FP SIG and Vector SIG

      • SFU item are motivated by AI activation functions, DSP, and other specialized applications

  • Non-ISA

    • Opensource IOMMU implementation (#1) available at University of Minho (Portugal): link | source

      • Discussion around reference implementations occurred: RISC-V remains focused on being a standards body

    • I/D Cache coherency (#2) started under J-ext TG (moved to SIG). FT extension being explored as starting point. More work expected. (Should move to ISA, 3-6)

    • HPE being worked (#4)

    • User mode timer and interrupts (#5) has been raised through HP IO SIG.

    • Documentation (#7) being shared with TSC, CSC, Doc SIG.

      • A lot of work to do around normative rule declaration. CSC, UDB SIG, Doc SIG building a proposal.

      • CSC and TSC will need to collaborate on the list to achieve successful results.

    • Side-channel (#10) also includes work on Speculation Barriers (new TG)

  • Profiles

    • Next RVA Profile (#1)

      • Next major 2+ years away (Profiles SIG)

      • Expect 1-2 minor releases pending

    • Security Profile (#2) discussion

      • Being built as “Security Model” specification

      • Might need a platform to build extensions + Security Model

    • RVA23+ challenges… (#3)

      • OSs tend to do WARL discovery making VM migration difficult

    • Debug/Trace and Interrupt Profiles (#6)

      • This is a request for inclusion of items in this area

      • Debug and interrupts are more of a Platform level consideration

      • These are key areas for Certification work as well

  • Platforms

    • #2 not solvable by RISC-V

    • #3 needs more refinement to clarify which areas of Automotive

    • Appears #4 not solvable by RISC-V as written, but may need more deep look

      • Discussion: are there areas of standardization that might not be purely RISC-V centric but still beneficial, e.g. AXI, AMBA.

      • Would recommend SOC Infrastructure HC lead this look

    • Certification Authority (#8) for software signing

      • Certificate to be provided to Secure Boot.

      • @Andrea Gallo will help drive this considering the strategic and operational fronts.

    • #9 Platform Systems