2025-12-03 TSC Meeting

2025-12-03 TSC Meeting

Date

Dec 3, 2025

Disclosures

05092025-RVI-Disclosures-Female.mp4

 

Participants

Voters | Quorum Required - 16

Name

Affiliation

Attended

Join Time (U.S. ET)

Leave Time
(U.S. ET)

Name

Affiliation

Attended

Join Time (U.S. ET)

Leave Time
(U.S. ET)

1

Austin (Jianlin) Gao

Tencent

 

 

 

2

Avi Timor

Google

X

10:07 AM

11:18 AM

3

Charlie Su

Andes

X

10:06 AM

12:03 PM

4

David Brash

Rivos Inc.

X

10:02 AM

12:03 PM

5

David Chen

Stream Computing

 

 

 

6

David Weaver

Akeana

X

10:01 AM

12:03 PM

7

Earl Killian - Unpriv IC

Aril Inc.

X

10:05 AM

12:02 PM

8

Erich Focht

Openchip

X

10:33 AM

11:53 AM

9

Feiming Wang

Sanechips/ZTE

X

10:14 AM

12:03 PM

10

Frans Sijstermans

Nvidia

 

 

 

11

Greg Favor - TSC Chair

Ventana Micro Systems

X

10:04 AM

12:03 PM

12

Guido Costa Souza

Brazilian Ministry of Science

 

 

 

13

Guohua Chen

ESWIN

 

 

 

14

Guy Lemieux - Com/Individ Elected Rep

Individual

X

10:59 AM

12:03 PM

15

Hongbin Zhang

ISCAS

X

9:59 AM

12:03 PM

16

Jian Zhang

Beijing Institute of Open Source Chip

 

 

 

17

Kan Shi

ICT CAS

 

 

 

18

Ken Dockser - Strategic Elected Rep

Tenstorrent

X

10:07 AM

12:03 PM

19

Krste Asanovic

SiFive

X

10:04 AM

12:03 PM

20

Manu Gulati

Qualcomm

X

10:04 AM

12:03 PM

21

Marcel Tromp

Infineon

X

10:03 AM

11:04 AM

22

Nambi Ju - Technology HC Vice-chair

Individual

 

 

 

23

Paul Holt

Synopsys

 

 

 

24

Peter Chun

Huawei

 

 

 

25

Philipp Tomsich - TSC Vice-chair

VRULL

X

10:02 AM

12:03 PM

26

Eudora Zhu for Siqi Zhao

Alibaba Cloud

X

10:00 AM

12:03 PM

27

Tariq Kurd - Strategic Elected Rep

Codasip

X

10:02 AM

12:03 PM

28

Tom Zhao

Phytium

 

 

 

29

Wei Wu

Kubuds

X

10:01 AM

11:13 AM

30

Zhangxi Tan

RIOS

 

 

 

18 Voting Members present

Non-Voters

Name

Affiliation

Attended

Name

Affiliation

Attended

Andrew Dellow

Qualcomm, Inc.

X

Andrew Waterman

SiFive

 

Anup Patel

Ventana Micro Systems

X

Derek Hower

Qualcomm, Inc.

X

Jiangang Duan

Intel

 

Bruce Ableidinger

MIPS

X

Ravi Sahita

Rivos Inc

X

Vedvyas Shanbhogue

Rivos Inc

X

Jay Gamoneda

NXP

X

Andrea Gallo

RISC-V International

X

Austin Blackstone

RISC-V International

X

Bill Traynor

RISC-V International

X

Greg Sterling

RISC-V International

X

Kersten Richter

RISC-V International

 

Jeff Scheel

RISC-V International

X

Rafael Sene

RISC-V International

X

Tom Gall

RISC-V International

X

Holger Blasum

SYSGO

X

Daniel Gracia Perez

Thales

X

Radim Krčmář

Ventana Micro Systems

X

Agenda

Approve November 5 (link) and November 12 Overflow Meeting minutes (link) - 5 min
Sail Yearly Update (Jeff, Prashanth) - 15 min
Continuation: Golden Reference Model Survey (Derek Hower, Qualcomm) - 30 min
Functional Safety White Paper (Daniel Gracia) - 20 min
Continuation: Updated RISC-V Policies (Ken Dockser) - 30 min

Overflow Meeting Topics (next week)

New PoW: Logic Analyzer Trace Task Group | Sajosh Janarthanam (Tenstorrent), Eric Rentschler (Tenstorrent), Jay Gamoneda (NXP), Robert Chyla (MIPS), Rejeesh SB (Ashling) - 20 min
Task Group Extension Justification

Presentations

Title

Presenter

File

Title

Presenter

File

1

Sail Update - 4Q2025

Jeff Scheel

 

2

Golden Reference Model Survey

Derek Hower

 

3

Updated Policies & Procedures

Ken Dockser

 

4

Functional Safety White Paper

Daniel Gracia

 

Votes

Quorum Status: Met
Vote Record

  • Agenda Item or Motion: Approve November 5 and November 12 overflow meeting minutes per above

  • Motion Made By: David Weaver

  • Motion Seconded By: Ken Dockser

Voting Results:

  • In Favor: 18 - Google (Avi), Andes (Charlie), Rivos Inc. (David B.), Akeana (David W.), Aril Inc. (Earl), Openchip (Erich), Sanechips/ZTE (Feiming), Ventana Micro Systems (Greg), Individual (Guy), ISCAS (Hongbin), Tenstorrent (Ken), SiFive (Krste), Qualcomm (Manu), Infineon (Marcel),
    VRULL (Philipp), Alibaba (Eudora), Codasip (Tariq), Kubuds (Wei)

  • Opposed: None

  • Abstentions: None

Outcome: Passed at 0:45 into the meeting

Additional Notes:

Notes & Action Items

Meeting recording and transcript: link

Meeting Summary

Sail Yearly Update

The discussion focused on the annual update of the RISC-V Sail project, presented by Jeff Scheel. The community has made significant progress, with binary releases now available every 3-6 months and a CI system in place. They completed 17 new extensions and reduced their backlog from 57 to 27 PRs. Configuration work for RVA23 certification has been completed, and the mandatory gaps have been reduced to 1.1 PY and 13 PRs. The team is now focusing on privilege extensions like hypervisor and debug. Jeff mentioned that the balance between paid resources and volunteers has helped accelerate contributions. The conversation ended with a discussion on making RISC-V Sail model code more consumable, potentially through an online documentation system.

The group discussed the need to track and address inconsistencies between different implementations of specifications, particularly between Sail and ACTs. Jeff agreed to investigate the process for handling clarifications in ISA specifications and ensure Sail and ACTs stay in sync. The team also discussed creating a centralized system for tracking clarifications and updates to the ISA manual, with a suggestion to use GitHub issues labeled appropriately.

Continuation: Golden Reference Model Survey

The discussion focused on reviewing and refining a survey designed to gather input from members on the Golden Reference Model's priorities and future development. Derek presented version 4 of the survey, which included updated questions addressing controversial topics from previous versions. Greg and Manu proposed using a ranking system to determine priorities, with Greg suggesting a flexible point allocation method. The group discussed the survey's distribution by the ISA Infrastructure HC and its potential review by the Golden Model TG and TSC. Ken inquired about the Golden Model SIG's internal priorities, which Rafael clarified is not a SIG but a TG led by staff.

The team discussed a survey about Golden Reference Models (GRMs) and their features. Ken requested to avoid initialisms (acronymns). They reviewed questions about the importance of various GRM features, including instruction set simulators, documentation generation, formal analysis, and artifact generation for downstream projects. Derek explained that they want to generate human-readable documentation from GRM sources to reduce the need to keep multiple specifications in sync. Krste warned against trying to design a system through surveys, suggesting instead that they should present concrete proposals for different tool organizations and let people provide feedback about them.

The group discussed the approach to evaluating tool proposals, with Krste emphasizing the need for concrete, complete proposals rather than surveys, as surveys alone cannot reach concrete conclusions. They agreed that different people should put together different proposals capturing all important features, which would then be reviewed and potentially iterated upon. The discussion also touched on the need for a complete tool flow rather than focusing solely on the Golden Reference Model (SAIL), with Krste noting that different proposals could include SAIL as one component among others.

Functional Safety White Paper

Daniel presented a presentation about the functional safety white paper that provides an overview of safety mechanisms and processes, identifies existing RISC-V specifications that can be used for safety solutions, and offers recommendations for implementation. Greg and Philipp asked questions about whether the white paper could serve as a checklist or catalog of requirements for new specifications, but Daniel explained that safety domains are too diverse to provide a single comprehensive set of requirements.

Daniel presented a white paper on functional safety in RISC-V, which is split into two documents: a public white paper detailing current functional safety coverage and a separate document highlighting future recommendations for the TSC. The white paper covers topics like caches, performance counters, quality of service, redundancy, and error reporting, with existing RISC-V solutions discussed for each area. Daniel noted that redundancy and error detection/correction are not standardized in RISC-V but are not identified as gaps, while quality of service is addressed at the system level.

The discussion focused on the white paper discussion about error correction codes and redundancy mechanisms in RISC-V architecture. Daniel explained that while other architectures provide solutions for dual-core lockstep and TMR at the platform level, RISC-V does not have specific ISA-level guidance. The group discussed next steps, including continuing review and feedback on the paper before the holidays, with formal TSC approval to follow. Jeff mentioned that after the gap analysis is complete, they will work with Daniel to determine what actions are needed and how to present the findings to task group chairs.

Detailed Minutes

  • Sail Yearly Update

    • This is the 3rd yearly update of Sail progress.

    • Slides from previous presentations are in the backup of the presentation. The format of certain slides have been reused for bridging.

    • The 2025 progress was impressive from a community contribution perspective.

    • Additional RVI Staffing (contractor new for 2025) has provided a good balance between member contributions and community needs

    • Progress on RVA23 has nearly completed all Unpriv instructions (a few late configuration items were found recently and added, see purple items). Focus turning to Priv.

    • A few large items like Debug and Hypervisor remain but are starting to be included in small chunks.

    • Action Item:

      Readiness for RVI20 by Sail (Jeff, Prashanth)
      Process for handling ISA Clarifications as they apply to Sail (Jeff, Prashanth)
      ISA clarifications agreed to by ARC need to ensure that impacts to Sail and ACT are understood and addressed by issue raiser. (Greg, Krste, ARC)
  • Continuation: Golden Reference Model Survey

    • Version 4 of survey doc is available and has been reviewed

    • Reminder that this a proposal to get information on how the Golden Models are being used.

    • Discussion:

      • Question 4:

        • Has been slimmed down from previous version (version 3).

        • There’s not cross-ranking across all things so how do we prevent everything from being a 1 or a 5.

        • Does the ISA Infra HC have expected priorities for these items?

        • Perhaps we want priorities from the CSC?

        • Suggest we remove the TLAs.

      • Question 5:

        • GRM used as a term because of the fact that they can generate simulators.

        • What flavors of documentation is intended?
          Answer: Ops codes, formal description, etc. Want to

        • Design by survey is difficult is accomplish. The alternative approach is to put a couple proposals and solicit feedback. The design work is inevitable in this process.

        • The survey is attempting to prioritize the “whats”. An alternate technique is to declare the “whats” and review them. The advantage of the latter is to help people understand the environment.

      • Question 6: Simply focused on use

        • Each simulator/model has a role and we need to ensure synergy and appropriate usage.

    • Next steps:

      Call for proposals need to be articulated for the flow. (Derek and Manu)
      Note: there has been some work in this space between Derek and Andrea.
      Review of flow and proposals, starting at email but back into TSC meeting as-needed. (Derek)
  • Functional Safety White Paper

    • Presentation included here: link

    • Discussion:

    RISC-V International